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ADM1066ACPZ データシート(PDF) 7 Page - Analog Devices

部品番号 ADM1066ACPZ
部品情報  Super Sequencer with Margining Control and Auxiliary ADC Inputs
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メーカー  AD [Analog Devices]
ホームページ  http://www.analog.com
Logo AD - Analog Devices

ADM1066ACPZ データシート(HTML) 7 Page - Analog Devices

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ADM1066
Rev. E | Page 7 of 32
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
DIGITAL INPUTS (VXx, A0, A1)
Input High Voltage, VIH
2.0
V
Maximum VIN = 5.5 V
Input Low Voltage, VIL
0.8
V
Maximum VIN = 5.5 V
Input High Current, IIH
−1
μA
VIN = 5.5 V
Input Low Current, IIL
1
μA
VIN = 0 V
Input Capacitance
5
pF
Programmable Pull-Down
Current, IPULL-DOWN
20
μA
VDDCAP = 4.75 V, TA = 25°C, if known logic state is required
SERIAL BUS DIGITAL INPUTS
(SDA, SCL)
Input High Voltage, VIH
2.0
V
Input Low Voltage, VIL
0.8
V
Output Low Voltage, VOL2
0.4
V
IOUT = −3.0 mA
SERIAL BUS TIMING3
Clock Frequency, fSCLK
400
kHz
Bus Free Time, tBUF
1.3
μs
Start Setup Time, tSU;STA
0.6
μs
Stop Setup Time, tSU;STO
0.6
μs
Start Hold Time, tHD;STA
0.6
μs
SCL Low Time, tLOW
1.3
μs
SCL High Time, tHIGH
0.6
μs
SCL, SDA Rise Time, tR
300
ns
SCL, SDA Fall Time, tF
300
ns
Data Setup Time, tSU;DAT
100
ns
Data Hold Time, tHD;DAT
5
ns
Input Low Current, IIL
1
μA
VIN = 0 V
SEQUENCING ENGINE TIMING
State Change Time
10
μs
1 At least one of the VH, VPx pins must be ≥3.0 V to maintain the device supply on VDDCAP.
2 Specification is not production tested but is supported by characterization data at initial product release.
3 Timing specifications are guaranteed by design and supported by characterization data.


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