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AM188EM-33VIW データシート(PDF) 3 Page - InnovASIC, Inc |
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AM188EM-33VIW データシート(HTML) 3 Page - InnovASIC, Inc |
3 / 146 page IA186EM/IA188EM Data Sheet 8-Bit/16-Bit Microcontrollers February 25, 2011 IA211050831-19 http://www.Innovasic.com UNCONTROLLED WHEN PRINTED OR COPIED Customer Support: Page 3 of 146 1-888-824-4184 ® TABLE OF CONTENTS List of Figures ..................................................................................................................................8 List of Tables ...................................................................................................................................9 Conventions ...................................................................................................................................12 Acronyms and Abbreviations ........................................................................................................13 1. Introduction...........................................................................................................................14 1.1 General Description.....................................................................................................14 1.2 Features .......................................................................................................................14 2. Packaging , Pin Descriptions, and Physical Dimensions......................................................15 2.1 Packages and Pinouts ..................................................................................................15 2.1.1 IA186EM TQFP Package ...............................................................................16 2.1.2 IA188EM TQFP Package ...............................................................................19 2.1.3 TQFP Physical Dimensions ............................................................................22 2.1.4 IA186EM PQFP Package ...............................................................................23 2.1.5 IA188EM PQFP Package ...............................................................................26 2.1.6 PQFP Physical Dimensions ............................................................................29 2.2 Pin Descriptions ..........................................................................................................30 2.2.1 a19/pio9, a18/pio8, a17/pio7, a16–a0—Address Bus (synchronous outputs with tristate) .......................................................................................30 2.2.2 ad15–ad8 (IA186EM)—Address/data bus (level-sensitive synchronous inouts with tristate) ....................................................................30 2.2.3 ad7–ad0—Address/Data bus (level-sensitive synchronous inouts with tristate) ............................................................................................................30 2.2.4 ao15–ao8 (IA188EM)—Address-only bus (level-sensitive synchronous outputs with tristate) ..................................................................30 2.2.5 ale—Address Latch Enable (synchronous output) .........................................31 2.2.6 ardy—Asynchronous Ready (level-sensitive asynchronous input) ................31 2.2.7 bhe_n/aden_n (IA186EM)—Bus High Enable (synchronous output with tristate)/Address Enable (input with internal pull-up)............................31 2.2.8 clkouta—Clock Output A (synchronous output) ............................................32 2.2.9 clkoutb—Clock Output B (synchronous output) ............................................32 2.2.10 den_n/pio5—Data Enable Strobe (synchronous output with tristate) ............32 2.2.11 drq1/pio12–drq0/pio13—DMA Requests (synchronous level-sensitive inputs) .............................................................................................................32 2.2.12 dt/r_n/pio4—Data Transmit or Receive (synchronous output with tristate) ............................................................................................................32 2.2.13 gnd—Ground ..................................................................................................32 2.2.14 hlda—Bus Hold Acknowledge (synchronous output) ....................................33 2.2.15 hold—Bus Hold Request (synchronous level-sensitive input).......................33 2.2.16 int0—Maskable Interrupt Request 0 (asynchronous input)............................33 2.2.17 int1/select_n—Maskable Interrupt Request 1/Slave Select (both are asynchronous inputs) ......................................................................................33 |
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