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CAT1021LI-25-G データシート(PDF) 6 Page - ON Semiconductor

部品番号 CAT1021LI-25-G
部品情報  Supervisory Circuits with I2C Serial 2k-bit CMOS
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メーカー  ONSEMI [ON Semiconductor]
ホームページ  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

CAT1021LI-25-G データシート(HTML) 6 Page - ON Semiconductor

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CAT1021, CAT1022, CAT1023
Doc. No. MD-3009 Rev. P
6
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
RESET CIRCUIT AC CHARACTERISTICS
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
tPURST
Power-Up Reset Timeout
Note 2
130
200
270
ms
tRDP
VTH to RESET output Delay
Note 3
5
µs
tGLITCH
VCC Glitch Reject Pulse Width
Note 4, 5
30
ns
MR Glitch
Manual Reset Glitch Immunity
Note 1
100
ns
tMRW
MR Pulse Width
Note 1
5
µs
tMRD
MR Input to RESET Output Delay
Note 1
1
µs
tWD
Watchdog Timeout
Note 1
1.0
1.6
2.1
sec
POWER-UP TIMING
(5), (6)
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
tPUR
Power-Up to Read Operation
270
ms
tPUW
Power-Up to Write Operation
270
ms
AC TEST CONDITIONS
Parameter
Test Conditions
Input Pulse Voltages
0.2 x VCC to 0.8 x VCC
Input Rise and Fall times
10 ns
Input Reference Voltages
0.3 x VCC , 0.7 x VCC
Output Reference Voltages
0.5 x VCC
Output Load
Current Source: IOL = 3 mA; CL = 100 pF
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Reference Test Method
Min
Max
Units
NEND
(5)
Endurance
MIL-STD-883, Test Method 1033
1,000,000
Cycles/Byte
TDR
(5)
Data Retention
MIL-STD-883, Test Method 1008
100
Years
VZAP
(5)
ESD Susceptibility
MIL-STD-883, Test Method 3015
2000
Volts
ILTH
(5)(7)
Latch-Up
JEDEC Standard 17
100
mA
Notes:
(1) Test Conditions according to “AC Test Conditions” table.
(2) Power-up, Input Reference Voltage VCC = VTH, Reset Output Reference Voltage and Load according to “AC Test Conditions” Table
(3) Power-Down, Input Reference Voltage VCC = VTH, Reset Output Reference Voltage and Load according to “AC Test Conditions” Table
(4) VCC Glitch Reference Voltage = VTHmin; Based on characterization data
(5) This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
(6) tPUR and tPUW are the delays required from the time VCC is stable until the specified memory operation can be initiated.
(7) Latch-up protection is provided for stresses up to 100mA on input and output pins from -1 V to VCC + 1 V.


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