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AD5203AN10 データシート(PDF) 10 Page - Analog Devices |
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AD5203AN10 データシート(HTML) 10 Page - Analog Devices |
10 / 12 page AD5203 –10– REV. 0 PROGRAMMING THE POTENTIOMETER DIVIDER Voltage Output Operation The digital potentiometer easily generates an output voltage proportional to the input voltage applied to a given terminal. For example connecting A–terminal to +5 V and B–terminal to ground produces an output voltage at the wiper which can be any value starting at zero volts up to 1 LSB less than +5 V. Each LSB of voltage is equal to the voltage applied across ter- minal AB divided by the 64 position resolution of the potenti- ometer divider. The general equation defining the output voltage with respect to ground for any given input voltage ap- plied to terminals AB is: VW(Dx) = Dx/64 × V AB + VB Operation of the digital potentiometer in the divider mode results in more accurate operation over temperature. Here the output voltage is dependent on the ratio of the internal resistors not the absolute value, therefore the drift improves to 20 ppm/ °C. DIGITAL INTERFACING The AD5203 contains a standard three-wire serial input control interface. The three inputs are clock (CLK), CS and serial data input (SDI). The positive-edge sensitive CLK input requires clean transitions to avoid clocking incorrect data into the serial input register. Standard logic families work well. If mechanical switches are used for product evaluation they should be de- bounced by a flip-flop or other suitable means. The Figure 35 block diagram shows more detail of the internal digital cir- cuitry. When CS is taken active low the clock loads data into the serial register on each positive clock edge, see Table III. AGND A1 W1 B1 VDD AD5203 CS CLK 6 D5 D0 EN ADDR DEC A1 A0 SDI DI SER REG D0 D5 SDO DO DGND A4 W4 B4 SHDN RS DAC LAT #1 R R D5 D0 DAC LAT #4 R R Figure 35. Block Diagram The serial-data-output (SDO) pin contains an open drain n-channel FET. This output requires a pull-up resistor in order to transfer data to the next package’s SDI pin. The pull-up resistor termination voltage may be larger than the VDD supply of the AD5203 SDO output device, e.g., the AD5203 could operate at VDD = 3.3 V and the pull-up for interface to the next device could be set at +5 V. This allows for daisy chaining sev- eral RDACs from a single processor serial data line. Clock pe- riod needs to be increased when using a pull-up resistor to the SDI pin of the following device in the series. Capacitive loading at the daisy chain node SDO-SDI between devices must be accounted for to successfully transfer data. When daisy chaining is used, the CS should be kept low until all the bits of every package are clocked into their respective serial registers insuring that the address bits and data bits are in the proper decoding location. This would require 16 bits of address and data comply- ing to the word format provided in Table I if two AD5203 four- channel RDACs are daisy chained. During shutdown, SHDN the SDO output pin is forced to the off (logic high state) to disable power dissipation in the pull-up resistor. See Figure 37 for equivalent SDO output circuit schematic. Table II. Input Logic Control Truth Table CLK CS RS SHDN Register Activity L L H H No SR effect, enables SDO pin. P L H H Shift one bit in from the SDI pin. The eighth previously entered bit is shifted out of the SDO pin. X P H H Load SR data into RDAC latch based on A1, A0 decode (Table III). X H H H No Operation. X X L H Sets all RDAC latches to midscale, wiper centered and SDO latch cleared. X H P H Latches all RDAC latches to 20H. X H H L Open circuits all Resistor A–termi- nals, connects W to B, turns off SDO output transistor. NOTE: P = positive edge, X = don’t care, SR = shift register. Table III. Address Decode Table A1 A0 Latch Decoded 0 0 RDAC#1 0 1 RDAC#2 1 0 RDAC#3 1 1 RDAC#4 |
同様の部品番号 - AD5203AN10 |
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同様の説明 - AD5203AN10 |
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