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AD7233AN データシート(PDF) 5 Page - Analog Devices

部品番号 AD7233AN
部品情報  LC2MOS 12-Bit Serial Mini-DIP DACPORT
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メーカー  AD [Analog Devices]
ホームページ  http://www.analog.com
Logo AD - Analog Devices

AD7233AN データシート(HTML) 5 Page - Analog Devices

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AD7233
REV. B
–5–
There are two ways in which the DAC latch and hence the ana-
log output may be updated. The status of the
LDAC input is
examined after
SYNC is taken low. Depending on its status, one
of two update modes is selected.
If
LDAC = 0 then the automatic update mode is selected. In
this mode the DAC latch and analog output are updated auto-
matically when the last bit in the serial data stream is clocked in.
The update thus takes place on the sixteenth falling SCLK edge.
If
LDAC = 1 then the automatic update is disabled and the
DAC latch is updated by taking
LDAC low any time after the
16-bit data transfer is complete. The update now occurs on the
falling edge of
LDAC. This facility is useful for simultaneous
update in multi-DAC systems. Note that the
LDAC input must
be taken back high again before the next data transfer is initiated.
SYNC
SCLK
SDIN
LDAC
RESET
16
COUNTER/
DECODER
GATING
SIGNAL
AUTO-UPDATE
CIRCUITRY
GATING
SCLK
DAC LATCH (12 BITS)
INPUT SHIFT REGISTER (16 BITS)
Figure 2. Simplified Loading Structure
DB15
DON’T CARE
DB14
DON’T CARE
DB13
DON’T CARE
DB12
DON’T CARE
DB11
MSB
DB1
DB0
LSB
t
2
t
1
t
4
t
5
t
3
t
6
t
7
t
8
SYNC
SCLK
SDIN
LDAC
Figure 3. Timing Diagram


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