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TPS65580PWPR データシート(PDF) 6 Page - Texas Instruments |
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TPS65580PWPR データシート(HTML) 6 Page - Texas Instruments |
6 / 28 page SW1 VIN VBST1 EN1 VFB2 EN3 GND VREG5 PGND1 6 VBST2 SW2 EN2 5 1 3 11 2 4 7 13 12 TPS65580 HTSSOP20 14 8 15 16 (PowerPAD) VFB1 VFB3 VBST3 SW3 10 9 17 18 19 20 PGND2 PGND3 PG VIN TPS65580 SLVSC29 – SEPTEMBER 2013 www.ti.com DEVICE INFORMATION HTSSOP PACKAGE (TOP VIEW) PIN FUNCTIONS(1) PIN I/O DESCRIPTION NAME TSSOP20 VIN 1,2 I Power input and connects to both high side NFET drains. Supply Input for 5.5V linear regulator. VBST1, VBST2, Supply input for high-side NFET gate drive circuit. Connect 0.1µF ceramic capacitor between 3, 14, 20 I VBST3 VBSTx and SWx pins. An internal diode is connected between VREG5 and VBSTx SW1, SW2, Switch node connections for both the high-side NFETs and low–side NFETs. Input of current 4,15,19 I/O SW3 comparator. PGND1, PGND2, 5,16,18 I/O Ground returns for low-side MOSFETs. Input of current comparator. PGND3 Output of 5.5V linear regulator. Bypass to GND with a high-quality ceramic capacitor of at least VREG5 6 O 1.0µF. VREG5 is active when ENx is high level. PG 7 O Open drain power good output. Low means the output voltage is out of regulation. EN1, EN2, EN3 8,13,17 I Enable. Pull High to according converter. VFB1, VFB2, 9,11,12 I D-CAP2 feedback inputs. Connect to output voltage with resistor divider. VFB3 GND 10 I/O Signal GND. Connect sensitive VFBx returns to GND at a single point. Exposed Thermal pad of the package. Must be soldered to achieve appropriate dissipation. Must be Back side I/O Thermal Pad connected to GND. (1) x means either 1, 2 or 3, VFBx means VFB1, VFB2 or VFB3. 6 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS65580 |
同様の部品番号 - TPS65580PWPR |
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同様の説明 - TPS65580PWPR |
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