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74AHCT574PW データシート(PDF) 5 Page - NXP Semiconductors |
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74AHCT574PW データシート(HTML) 5 Page - NXP Semiconductors |
5 / 18 page 74AHC_AHCT574_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 24 January 2008 5 of 18 NXP Semiconductors 74AHC574; 74AHCT574 Octal D-type flip-flop; positive edge-trigger; 3-state 6. Functional description [1] H = HIGH voltage level; h = HIGH voltage level one setup time prior to the HIGH-to-LOW CP transition; L = LOW voltage level; l = LOW voltage level one setup time prior to the HIGH-to-LOW CP transition; Z = high-impedance OFF-state; ↑ = LOW-to-HIGH clock transition. 7. Limiting values [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] Ptot derates linearly with 8 mW/K above 70 °C. [3] Ptot derates linearly with 5.5 mW/K above 60 °C. [4] Ptot derates linearly with 4.5 mW/K above 60 °C. Table 3. Function table[1] Operating mode Input Internal flip-flop Output OE CP Dn Qn Load and read register L ↑ lL L L ↑ hH H Load register and disable output H ↑ lL Z H ↑ hH Z Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit VCC supply voltage −0.5 +7.0 V VI input voltage −0.5 +7.0 V IIK input clamping current VI < −0.5 V [1] −20 - mA IOK output clamping current VO < −0.5 V or VO >VCC + 0.5 V [1] - ±20 mA IO output current VO = −0.5 V to (VCC + 0.5 V) - ±25 mA ICC supply current - 75 mA IGND ground current −75 - mA Tstg storage temperature −65 +150 °C Ptot total power dissipation Tamb = −40 °C to +125 °C SO20 package [2] - 500 mW TSSOP20 package [3] - 500 mW DHVQFN20 package [4] - 500 mW |
同様の部品番号 - 74AHCT574PW |
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同様の説明 - 74AHCT574PW |
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