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AD7142ACPZ-500RL7 データシート(PDF) 8 Page - Analog Devices |
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AD7142ACPZ-500RL7 データシート(HTML) 8 Page - Analog Devices |
8 / 73 page AD7142 Rev. A | Page 7 of 72 I2C TIMING SPECIFICATIONS (AD7142-1) TA = −40°C to +85°C; VDRIVE = 1.65 V to 3.6 V; AVCC, DVCC = 2.6 V to 3.6 V, unless otherwise noted. Sample tested at 25°C to ensure compliance. All input signals timed from a voltage level of 1.6 V. Table 5. I2C Timing Specifications1 Parameter Limit Unit Description fSCLK 400 kHz max t1 0.6 μs min Start condition hold time, tHD; STA t2 1.3 μs min Clock low period, tLOW t3 0.6 μs min Clock high period, tHIGH t4 100 ns min Data setup time, tSU; DAT t5 300 ns min Data hold time, tHD; DAT t6 0.6 μs min Stop condition setup time, tSU; STO t7 0.6 μs min Start condition setup time, tSU; STA t8 1.3 μs min Bus free time between stop and start conditions, tBUF tR 300 ns max Clock/data rise time tF 300 ns max Clock/data fall time 1 Guaranteed by design, not production tested. SCLK SDATA tR tF t2 t5 t1 t3 t4 STOP START STOP START t7 t6 t1 t8 Figure 4. I2C Detailed Timing Diagram |
同様の部品番号 - AD7142ACPZ-500RL7 |
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同様の説明 - AD7142ACPZ-500RL7 |
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