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AD7225KR-REEL データシート(PDF) 9 Page - Analog Devices |
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AD7225KR-REEL データシート(HTML) 9 Page - Analog Devices |
9 / 24 page AD7225 Rev. C | Page 9 of 24 CIRCUIT INFORMATION DIGITAL-TO-ANALOG SECTION The AD7225 contains four identical, 8-bit voltage mode digital- to-analog converters. Each DAC has a separate reference input. The output voltages from the converters have the same polarity as the reference voltages, allowing single-supply operation. A novel DAC switch pair arrangement on the AD7225 allows a refer- ence voltage range from 2 V to 12.5 V on each reference input. Each DAC consists of a highly stable, thin-film, R-2R ladder and eight high speed NMOS, single-pole, double-throw switches. The simplified circuit diagram for Channel A is shown in Figure 10. Note that AGND is common to all four DACs. VOUTA 2R DB7 2R DB6 2R DB5 2R 2R DB0 R R R VREFA AGND SHOWN FOR ALL 1s ON DAC Figure 10. Digital-to-Analog Simplified Circuit Diagram The input impedance at any of the reference inputs is code dependent and can vary from 11 kΩ minimum to infinity. The lowest input impedance at any reference input occurs when that DAC is loaded with Digital Code 01010101. Therefore, it is important that the reference presents a low output impedance under changing load conditions. The nodal capacitance at the reference terminals is also code dependent and typically varies from 15 pF to 35 pF. Each VOUTx pin can be considered a digitally programmable voltage source with an output voltage of VOUTX = DX × VREFX where DX is a fractional representation of the digital input code and can vary from 0 to 255/256. The output impedance is that of the output buffer amplifier. OP AMP SECTION Each voltage mode DAC output is buffered by a unity gain noninverting CMOS amplifier. This buffer amplifier is capable of developing 10 V across a 2 kΩ load and can drive capacitive loads of 3300 pF. The AD7225 can be operated single or dual supply; operating with dual supplies results in enhanced performance in some parameters that cannot be achieved with single-supply opera- tion. In single-supply operation (VSS = 0 V = AGND), the sink capability of the amplifier, which is normally 400 μA, is reduced as the output voltage nears AGND. The full sink capability of 400 μA is maintained over the full output voltage range by tying VSS to −5 V. This is shown in Figure 11. Settling time for negative-going output signals approaching AGND is similarly affected by VSS. Negative-going settling time for single-supply operation is longer than for dual-supply opera- tion. Positive-going settling time is not affected by VSS. 500 400 300 200 100 0 0 10 8 6 4 2 VOUT (V) VSS = –5V VSS = 0V VDD = +15V TA = 25°C Figure 11. Variation of ISINK with VOUT Additionally, the negative VSS gives more headroom to the output amplifiers, which results in better zero code perfor- mance and improved slew rate at the output than can be obtained in the single-supply mode. DIGITAL INPUTS SECTION The AD7225 digital inputs are compatible with either TTL or 5 V CMOS levels. All logic inputs are static protected MOS gates with typical input currents of less than 1 nA. Internal input protection is achieved by an on-chip distributed diode between DGND and each MOS gate. To minimize power supply currents, it is recommended that the digital input voltages be driven as close to the supply rails (VDD and DGND) as practi- cally possible. |
同様の部品番号 - AD7225KR-REEL |
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同様の説明 - AD7225KR-REEL |
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