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AM28F010-200FC データシート(PDF) 6 Page - Advanced Micro Devices

部品番号 AM28F010-200FC
部品情報  1 Megabit (128 K x 8-Bit) CMOS 12.0 Volt, Bulk Erase Flash Memory
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メーカー  AMD [Advanced Micro Devices]
ホームページ  http://www.amd.com
Logo AMD - Advanced Micro Devices

AM28F010-200FC データシート(HTML) 6 Page - Advanced Micro Devices

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Am28F010
PIN DESCRIPTION
A0–A16
Address Inputs for memory locations. Internal latches
hold addresses during write cycles.
CE# (E#)
Chip Enable active low input activates the chip’s con-
trol logic and input buffers. Chip Enable high will dese-
lect the device and operates the chip in stand-by mode.
DQ0–DQ7
Data Inputs during memor y write cycles. Internal
latches hold data during write cycles. Data Outputs
during memory read cycles.
NC
No Connect-corresponding pin is not connected
internally to the die.
OE# (G#)
Output Enable active low input gates the outputs of the
device through the data buffers during memory read
cycles. O utput Enable is high dur ing command
sequencing and program/erase operations.
VCC
Power supply for device operation. (5.0 V
± 5% or 10%)
VPP
Program voltage input. VPP must be at high voltage in
order to write to the command register. The command
register controls all functions required to alter the mem-
ory array contents. Memory contents cannot be altered
when VPP ≤ VCC +2 V.
VSS
Ground
WE# (W#)
Write Enable active low input controls the write function
of the command register to the memory array. The tar-
get address is latched on the falling edge of the Write
Enable pulse and the appropriate data is latched on the
rising edge of the pulse. Write Enable high inhibits
writing to the device.


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同様の説明 - AM28F010-200FC

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