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ST16C654CQ64 データシート(PDF) 4 Page - Exar Corporation |
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ST16C654CQ64 データシート(HTML) 4 Page - Exar Corporation |
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4 / 51 page  ST16C654/654D xr 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO REV. 5.0.2 4 PIN DESCRIPTIONS Pin Description NAME 64-LQFP PIN # 68-PLCC PIN# 100-QFP PIN # TYPE DESCRIPTION DATA BUS INTERFACE A2 A1 A0 22 23 24 32 33 34 37 38 39 I Address data lines [2:0]. These 3 address lines select one of the internal registers in UART channel A-D during a data bus transac- tion. D7 D6 D5 D4 D3 D2 D1 D0 60 59 58 57 56 55 54 53 5 4 3 2 1 68 67 66 95 94 93 92 91 90 89 88 I/O Data bus lines [7:0] (bidirectional). IOR# (VCC) 40 52 66 I When 16/68# pin is at logic 1, the Intel bus interface is selected and this input becomes read strobe (active low). The falling edge insti- gates an internal read cycle and retrieves the data byte from an internal register pointed by the address lines [A2:A0], puts the data byte on the data bus to allow the host processor to read it on the ris- ing edge. When 16/68# pin is at logic 0, the Motorola bus interface is selected and this input is not used and should be connected to VCC. IOW# (R/W#) 9 18 15 I When 16/68# pin is at logic 1, it selects Intel bus interface and this input becomes write strobe (active low). The falling edge instigates the internal write cycle and the rising edge transfers the data byte on the data bus to an internal register pointed by the address lines. When 16/68# pin is at logic 0, the Motorola bus interface is selected and this input becomes read (logic 1) and write (logic 0) signal. CSA# (CS#) 7 16 13 I When 16/68# pin is at logic 1, this input is chip select A (active low) to enable channel A in the device. When 16/68# pin is at logic 0, this input becomes the chip select (active low) for the Motorola bus interface. CSB# (A3) 11 20 17 I When 16/68# pin is at logic 1, this input is chip select B (active low) to enable channel B in the device. When 16/68# pin is at logic 0, this input becomes address line A3 which is used for channel selection in the Motorola bus interface. CSC# (A4) 38 50 64 I When 16/68# pin is at logic 1, this input is chip select C (active low) to enable channel C in the device. When 16/68# pin is at logic 0, this input becomes address line A4 which is used for channel selection in the Motorola bus interface. CSD# (VCC) 42 54 68 I When 16/68# pin is at logic 1, this input is chip select D (active low) to enable channel D in the device. When 16/68# pin is at logic 0, this input is not used and should be connected VCC. |
同様の部品番号 - ST16C654CQ64 |
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同様の説明 - ST16C654CQ64 |
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