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EP20K400 データシート(PDF) 76 Page - Altera Corporation |
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EP20K400 データシート(HTML) 76 Page - Altera Corporation |
76 / 117 page 76 Altera Corporation APEX 20K Programmable Logic Device Family Data Sheet Note to Tables 38 and 39: (1) These timing parameters are sample-tested only. Table 39. APEX 20KE External Bidirectional Timing Parameters Note (1) Symbol Parameter Conditions tINSUBIDIR Setup time for bidirectional pins with global clock at LAB adjacent Input Register tINHBIDIR Hold time for bidirectional pins with global clock at LAB adjacent Input Register tOUTCOBIDIR Clock-to-output delay for bidirectional pins with global clock at IOE output register C1 = 10 pF tXZBIDIR Synchronous Output Enable Register to output buffer disable delay C1 = 10 pF tZXBIDIR Synchronous Output Enable Register output buffer enable delay C1 = 10 pF tINSUBIDIRPLL Setup time for bidirectional pins with PLL clock at LAB adjacent Input Register tINHBIDIRPLL Hold time for bidirectional pins with PLL clock at LAB adjacent Input Register tOUTCOBIDIRPLL Clock-to-output delay for bidirectional pins with PLL clock at IOE output register C1 = 10 pF tXZBIDIRPLL Synchronous Output Enable Register to output buffer disable delay with PLL C1 = 10 pF tZXBIDIRPLL Synchronous Output Enable Register output buffer enable delay with PLL C1 = 10 pF |
同様の部品番号 - EP20K400 |
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同様の説明 - EP20K400 |
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