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EP20K400E データシート(PDF) 41 Page - Altera Corporation |
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EP20K400E データシート(HTML) 41 Page - Altera Corporation |
41 / 117 page Altera Corporation 41 APEX 20K Programmable Logic Device Family Data Sheet Figure 26. APEX 20KE Bidirectional I/O Registers Notes (1), (2) Notes to Figure 26: (1) This programmable delay has four settings: off and three levels of delay. (2) The output enable and input registers are LE registers in the LAB adjacent to the bidirectional pin. VCC OE[7..0] CLK[1..0] ENA[5..0] CLRn[1..0] Peripheral Control Bus CLRN/ PRN D Q ENA VCC 4 Dedicated Clock Inputs Chip-Wide Output Enable CLK[3..0] 4 12 VCC VCC Chip-Wide Reset Input Pin to Core Delay (1) Slew-Rate Control Open-Drain Output VCCIO Optional PCI Clamp Output Register t Delay Core to Output Register Delay Input Pin to Input Register Delay CLRN DQ ENA VCC Chip-Wide Reset Input Register Output Register CLRN DQ ENA Chip-Wide Reset VCC OE Register VCC 4 Dedicated Inputs Row, Column, FastRow, or Local Interconnect Clock Enable Delay (1) Input Pin to Core Delay (1) CO Input Pin to Core Delay (1) |
同様の部品番号 - EP20K400E |
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同様の説明 - EP20K400E |
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