ADM1166

Rev. 0 | Page 8 of 32

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

1

2

3

4

5

6

7

8

9

10

23

24

25

26

27

28

29

30

22

21

ADM1166

TOP VIEW

(Not to Scale)

VX1

VX2

VX3

VX4

VX5

VP1

VP2

VP3

VP4

VH

PDO1

NOTE

1. EXPOSED PAD SHOULD BE SOLDERED

TO THE BOARD FOR IMPROVED

MECHANICAL STABILITY.

PDO2

PDO3

PDO4

PDO5

PDO6

PDO7

PDO8

PDO9

PDO10

Figure 3. 40-Lead LFCSP Pin Configuration

NC = NO CONNECT

48

47

46

45

44

43

42

41

40

39

38

37

13

14

15

16

17

18

19

20

21

22

23

24

NC

1

VX1

2

VX2

3

VX3

4

VX4

5

VX5

6

VP1

7

VP2

8

VP3

9

NC

36

PDO1

35

PDO2

34

PDO3

33

PDO4

32

PDO5

31

PDO6

30

PDO7

29

PDO8

28

PDO9

27

PDO10

26

NC

25

ADM1166

TOP VIEW

(Not to Scale)

PIN 1

INDICATOR

Figure 4. 48-Lead TQFP Pin Configuration

Table 4. Pin Function Descriptions

Pin No.

40-Lead

LFCSP

48-Lead

TQFP

Mnemonic

Description

1, 12, 13, 24,

25, 36, 37, 48

NC

No Connect.

1 to 5

2 to 6

VX1 to VX5 (VXx)

High Impedance Inputs to Supply Fault Detectors. Fault thresholds can be set from 0.573 V to

1.375 V. Alternatively, these pins can be used as general-purpose digital inputs.

6 to 9

7 to 10

VP1 to VP4 (VPx)

Low Voltage Inputs to Supply Fault Detectors. Three input ranges can be set by altering the

input attenuation on a potential divider connected to these pins, the output of which

connects to a supply fault detector. These pins allow thresholds from 2.5 V to 6.0 V, from

1.25 V to 3.00 V, and from 0.573 V to 1.375 V.

10

11

VH

High Voltage Input to Supply Fault Detectors. Two input ranges can be set by altering the

input attenuation on a potential divider connected to this pin, the output of which connects

to a supply fault detector. This pin allows thresholds from 6.0 V to 14.4 V and from 2.5 V to 6.0 V.

11

14

AGND1

Ground Return for Input Attenuators.

12

15

REFGND1

Ground Return for On-Chip Reference Circuits.

13

16

REFIN

Reference Input for ADC. Nominally, 2.048 V. This pin must be driven by a reference voltage.

The on-board reference can be used by connecting the REFOUT pin to the REFIN pin.

14

17

REFOUT

Reference Output, 2.048 V. Typically connected to REFIN. Note that the capacitor must be

connected between this pin and REFGND. A 10 μF capacitor is recommended for this purpose.

15 to 20

18 to 23

DAC1 to DAC6

Voltage Output DACs. These pins default to high impedance at power-up.

21 to 30

26 to 35

PDO10 to PDO1

Programmable Driver Outputs.

31

38

PDOGND1

Ground Return for Driver Outputs.

32

39

VCCP

Central Charge-Pump Voltage of 5.25 V. A reservoir capacitor must be connected between

this pin and GND. A 10 μF capacitor is recommended for this purpose.

33

40

A0

Logic Input. This pin sets the seventh bit of the SMBus interface address.

34

41

A1

Logic Input. This pin sets the sixth bit of the SMBus interface address.

35

42

SCL

SMBus Clock Pin. Bidirectional, open-drain pin that requires external resistive pull-up.

36

43

SDA

SMBus Data Pin. Bidirectional, open-drain pin that requires external resistive pull-up.

37, 38

44, 45

AUX2, AUX1

Auxiliary, Single-Ended ADC Inputs.