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X1286V14T1 データシート(PDF) 11 Page - Intersil Corporation |
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X1286V14T1 データシート(HTML) 11 Page - Intersil Corporation |
11 / 25 page 11 FN8101.1 April 14, 2006 When there is a match, an alarm flag is set. The occur- rence of an alarm can be determined by polling the AL0 and AL1 bits or by enabling the IRQ output, using it as hardware flag. The alarm enable bits are located in the MSB of the particular register. When all enable bits are set to ‘0’, there are no alarms. – The user can set the X1286 to alarm every Wednes- day at 8:00 AM by setting the EDWn*, the EHRn* and EMNn* enable bits to ‘1’ and setting the DWAn*, HRAn* and MNAn* Alarm registers to 8:00 AM Wednesday. – A daily alarm for 9:30PM results when the EHRn* and EMNn* enable bits are set to ‘1’ and the HRAn* and MNAn* registers are set to 9:30 PM. *n = 0 for Alarm 0: N = 1 for Alarm 1 REAL TIME CLOCK REGISTERS Clock/Calendar Registers (SSEC, SC, MN, HR, DT, MO, YR) These registers depict BCD representations of the time. As such, SSEC (1/100 Second) range from 00 to 99, SC (Seconds) and MN (Minutes) range from 00 to 59, HR (Hour) is 1 to 12 with an AM or PM indicator (H21 bit) or 0 to 23 (with MIL=1), DT (Date) is 1 to 31, MO (Month) is 1 to 12, YR (Year) is 0 to 99. The SSEC register is read-only. Date of the Week Register (DW) This register provides a Day of the Week status and uses three bits DY2 to DY0 to represent the seven days of the week. The counter advances in the cycle 0-1-2-3-4-5-6-0-1-2-… The assignment of a numerical value to a specific day of the week is arbitrary and may be decided by the system software designer. The default value is defined as ‘0’. 24 Hour Time If the MIL bit of the HR register is 1, the RTC uses a 24-hour format. If the MIL bit is 0, the RTC uses a 12- hour format and H21 bit functions as an AM/PM indi- cator with a ‘1’ representing PM. The clock defaults to standard time with H21=0. Leap Years Leap years add the day February 29 and are defined as those years that are divisible by 4. Years divisible by 100 are not leap years, unless they are also divisi- ble by 400. This means that the year 2000 is a leap year, the year 2100 is not. The X1286 does not correct for the leap year in the year 2100. STATUS REGISTER (SR) The Status Register is located in the CCR memory map at address 003Fh. This is a volatile register only and is used to control the WEL and RWEL write enable latches, read two power status and two alarm bits. This register is separate from both the array and the Clock/Control Registers (CCR). Table 2. Status Register (SR) BAT: Battery Supply—Volatile This bit set to “1” indicates that the device is operating from VBACK, not VCC. It is a read-only bit and is set/reset by hardware (X1286 interally). Once the device begins operating from VCC, the device sets this bit to “0”. 0007 Alarm0 (EEPROM) Y2K0 Read-only - Default = 20h 20 20h 0006 DWA0 EDW0 0 0 0 0 DY2 DY1 DY0 0-6 00h 0005 YRA0 Unused - Default = RTC Year value (No EEPROM) – Future expansion 0004 MOA0 EMO0 0 0 A0G20 A0G13 A0G12 A0G11 A0G10 1-12 00h 0003 DTA0 EDT0 0 A0D21 A0D20 A0D13 A0D12 A0D11 A0D10 1-31 00h 0002 HRA0 EHR0 0 A0H21 A0H20 A0H13 A0H12 A0H11 A0H10 0-23 00h 0001 MNA0 EMN0 A0M22 A0M21 A0M20 A0M13 A0M12 A0M11 A0M10 0-59 00h 0000 SCA0 ESC0 A0S22 A0S21 A0S20 A0S13 A0S12 A0S11 A0S10 0-59 00h Table 1. Clock/Control Memory Map (Continued) Addr. Type Reg Name Bit Range 7 6 54 321 0 (optional) Addr 7 6 5 4 3 2 1 0 003Fh BAT AL1 AL0 0 0 RWEL WEL RTCF Default 0 0 0 0 0 0 0 1 X1286 |
同様の部品番号 - X1286V14T1 |
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同様の説明 - X1286V14T1 |
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