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LM25066IA データシート(PDF) 4 Page - Texas Instruments |
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LM25066IA データシート(HTML) 4 Page - Texas Instruments |
4 / 60 page LM25066I, LM25066IA SNVS824C – JUNE 2012 – REVISED MARCH 2013 www.ti.com Absolute Maximum Ratings (1) VIN, SENSE to GND (2) -0.3V to 24V GATE, FB, UVLO/EN, OVLO, PGD to GND (2) -0.3V to 20V Out to GND -1 to 20V SCL, SDA, SMBA, CL, CB, ADR0, ADR1, ADR2, VDD, VAUX, DIODE, RETRY to GND -0.3V to 6V VIN to SENSE -0.3V to +0.3V ESD Rating, Human Body Model(3) 2kV Storage Temperature -65°C to +150°C Junction Temperature +150°C (1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional. (2) The GATE pin voltage is typically 7.5V above VIN when the LM25066I/A is enabled. Therefore, the Absolute Maximum Rating of 24V for VIN and SENSE apply only when the LM25066I/A is disabled or for a momentary surge to that voltage since the Absolute Maximum Rating for the GATE pin is 20V. (3) The human body model is a 100 pF capacitor discharged through a 1.5 k Ω resistor into each pin. Operating Ratings VIN, SENSE, OUT voltage 2.9V to 17V VDD 2.9V to 5.5V Junction Temperature −40°C to +125°C Electrical Characteristics Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C to +85°C unless otherwise stated. Minimum and Maximum limits are specified through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the following conditions apply: VIN = 12V. See (1) and Symbol Parameter Conditions Min Typ Max Unit Input (VIN Pin) IIN-EN Input Current, enabled UVLO = 2V and OVLO = 0.7V 5.8 8 mA POR Power On Reset threshold at VIN VIN increasing 2.6 2.8 V PORHYS POREN Hysteresis VIN decreasing 150 mV VDD Regulator (VDD pin) VDD IVDD = 5mA, VIN = 12V 4.3 4.5 4.7 V IVDD = 5mA, VIN = 4.5V 3.5 3.9 4.3 V VDDILIM VDD Current Limit 25 45 mA UVLO/EN, OVLO Pins UVLOTH UVLO threshold VUVLO Falling 1.147 1.16 1.173 V UVLOHYS UVLO hysteresis current UVLO = 1V 18 23 28 µA UVLODEL UVLO delay Delay to GATE high 8 µs Delay to GATE low 20 UVLOBIAS UVLO bias current UVLO = 3V 1 µA OVLOTH OVLO threshold VOVLO rising 1.141 1.16 1.185 V OVLOHYS OVLO hysteresis current OVLO = 1V -28 -23 -18 µA OVLODEL OVLO delay Delay to GATE high 19 µs Delay to GATE low 9 OVLOBIAS OVLO bias current OVLO = 1V 1 µA Power Good (PGD pin) PGDVOL Output low voltage ISINK = 2 mA 25 60 mV PGDIOH Off leakage current VPGD = 17V 1 µA PGDDELAY Power Good Delay VFB to VPG 115 ns (1) Current out of a pin is indicated as a negative value. 4 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LM25066I LM25066IA |
同様の部品番号 - LM25066IA |
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同様の説明 - LM25066IA |
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