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ICS9248-168 データシート(PDF) 1 Page - Integrated Circuit Systems |
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ICS9248-168 データシート(HTML) 1 Page - Integrated Circuit Systems |
1 / 14 page Integrated Circuit Systems, Inc. ICS9248-168 Third party brands and names are the property of their respective owners. Block Diagram Functionality Pin Configuration 48-Pin 300mil SSOP Recommended Application: VIA KT133 style chipset Output Features: • 1 - Differential pair open drain CPU clocks • 1 - CPU clock @ 3.3V • 7 - SDRAM @ 3.3V • 8 - PCI @ 3.3V, • 1 - 48MHz, @ 3.3V fixed. • 1 - 24/48MHz @ 3.3V • 3 - REF @ 3.3V, 14.318MHz. Features: • Up to 153MHz frequency support • Support power management: CPU stop and Power down Mode from I 2C programming. • Spread spectrum for EMI control (± 0.25% to ± 0.6% center, or 0 to -0.5% or -1.0% down spread). • Uses external 14.318MHz crystal AMD - K7™ Clock Generator for Mobile System * Internal Pull-up Resistor of 120K to VDD 1 These outputs have double strength to drive 2 loads. 2 These outputs can be set to 1.5X strength through I 2C VDDREF X1 X2 *FS2/PCICLK_F *FS1/PCICLK0 VDDPCI GND PCICLK1 PCICLK2 PCICLK3 PCICLK4 PCICLK5 GND VDDPCI PCICLK6 *SDRAM_STOP# *PCI_STOP# BUFFER_IN AVDD GND GND *FS0/48MHZ *SEL24_48#/24_48MHz VDD48 REF0 REF REF2 GND GND VDD CPUCLK CPUCLKT0 CPUCLKC0 CPU_STOP#* PD#* SDRAM0 SDRAM1 VDDSDR GND SDRAM2 SDRAM3 GND VDDSDR SDRAM4 SDRAM5 SDRAM_F SCLK SDATA 1 2 2 2 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 2 S F1 S F0 S FU P CI C Pe g a t n e c r e P d a e r p S 000 0 0 . 0 0 13 3 . 3 3d a e r p S r e t n e C % 5 3 . 0 - / + 00 1 3 3 . 3 3 13 3 . 3 3d a e r p S r e t n e C % 5 3 . 0 - / + 01 0 0 0 . 0 0 13 3 . 3 3d a e r p S n w o D % 5 . 0 - o t 0 01 1 3 3 . 3 3 13 3 . 3 3d a e r p S n w o D % 5 . 0 - o t 0 10 0 0 0 . 0 0 13 3 . 3 3d a e r p S r e t n e C % 6 . 0 - / + 10 1 3 3 . 3 3 13 3 . 3 3d a e r p S r e t n e C % 6 . 0 - / + 11 0 0 0 . 0 90 0 . 0 3d a e r p S r e t n e C % 5 2 . 0 - / + 111 0 0 . 0 2 10 0 . 0 3d a e r p S r e t n e C % 5 2 . 0 - / + SEL24_48# SDATA SCLK FS (2:0) PD# CPU_STOP# PCI_STOP# SDRAM_STOP# BUFFER_IN PLL2 PLL1 Spread Spectrum 48MHz 24_48MHz SDRAM (5:0) PCICLK (6:0) PCICLK_F SDRAM_F CPUCLKT0 CPUCLK CPUCLKC0 X1 X2 XTAL OSC CPU DIVDER PCI DIVDER Stop Stop Stop Control Logic Config. Reg. / 2 REF (2:0) SDRAM DRIVER ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. 9248-168 Rev B 01/09/01 |
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同様の説明 - ICS9248-168 |
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