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TP28F010-150 データシート(PDF) 6 Page - Intel Corporation

部品番号 TP28F010-150
部品情報  28F010 1024K (128K X 8) CMOS FLASH MEMORY
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メーカー  INTEL [Intel Corporation]
ホームページ  http://www.intel.com
Logo INTEL - Intel Corporation

TP28F010-150 データシート(HTML) 6 Page - Intel Corporation

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28F010
E
6
290207-1
Figure 1. 28F010 Block Diagram
Table 1. Pin Description
Symbol
Type
Name and Function
A0–A16
INPUT
ADDRESS INPUTS for memory addresses. Addresses are internally
latched during a write cycle.
DQ0–DQ7
INPUT/OUTPUT
DATA INPUT/OUTPUT: Inputs data during memory write cycles; outputs
data during memory read cycles. The data pins are active high and float to
tri-state off when the chip is deselected or the outputs are disabled. Data is
internally latched during a write cycle
CE#
INPUT
CHIP ENABLE: Activates the device's control logic, input buffers, decoders
and sense amplifiers. CE# is active low; CE# high deselects the memory
device and reduces power consumption to standby levels.
OE#
INPUT
OUTPUT ENABLE: Gates the devices output through the data buffers
during a read cycle. OE# is active low.
WE#
INPUT
WRITE ENABLE: Controls writes to the control register and the array. Write
enable is active low. Addresses are latched on the falling edge and data is
latched on the rising edge of the WE# pulse.
Note: With VPP
≤ 6.5 V, memory contents cannot be altered.


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