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TP7C31BH データシート(PDF) 8 Page - Intel Corporation |
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TP7C31BH データシート(HTML) 8 Page - Intel Corporation |
8 / 16 page AUTOMOTIVE 80C31BH80C51BH87C51 ABSOLUTE MAXIMUM RATINGS Ambient Temperature Under Bias b40 Cto a125 C Storage Temperature b 65 Cto a150 C Voltage on EA VPP Pin to VSS 0V to a130V Voltage on Any Other Pin to VSS b 05V to a65V IOL per IO pin 15 mA Power Dissipation15W (Based on package heat transfer limitations not de- vice power consumption) Typical Junction Temperature (TJ) a 135 C (Based upon ambient temperature at a125 C) Typical Thermal Resistance Junction-to-Ambient (iJA) PDIP 75 CW PLCC 46 CW NOTICE This is a production data sheet The specifi- cations are subject to change without notice WARNING Stressing the device beyond the ‘‘Absolute Maximum Ratings’’ may cause permanent damage These are stress ratings only Operation beyond the ‘‘Operating Conditions’’ is not recommended and ex- tended exposure beyond the ‘‘Operating Conditions’’ may affect device reliability DC CHARACTERISTICS (TA eb40 Cto a125 C VCC e 5V g10% (5V g20% EPROM Only) VSS e 0V) Symbol Parameter Min Typ(1) Max Unit Test (87C5180C51BH) Conditions VIL Input Low Voltage (Except EA) b 05 02 VCCb025 V VIL1 Input Low Voltage to EA 0 02 VCCb045 V VIH Input High Voltage (Except XTAL1 RST) 02VCCa10 VCCa05 V VIH1 Input High Voltage (XTAL1 RST) 07 VCCa01 VCCa05 V VOL Output Low Voltage (Ports 1 2 3) 045(7) VIOL e 16 mA(2) VOL1 Output Low Voltage (Port 0 ALE PSEN) 045(7) VIOL e 32 mA(2) VOH Output High Voltage 24 V IOH eb60 mA (Ports 1 2 3 ALE PSEN) 09 VCC VIOH eb10 mA VOH1 Output High Voltage (Port 0 in 24 V IOH eb800 mA External Bus Mode) 09 VCC VIOH eb80 mA(3) IIL Logical 0 Input Current (Ports 1 2 3) b 75 m AVIN e 045 V ITL Logical 1-to-0 transition current b 750 m A (4) (Ports 1 2 3) ILI Input Leakage Current (Port 0) g 10 m AVIN e VIL or VIH ICC Power Supply Current Active Mode 12 MHz (5) 115 2520 mA Idle Mode 12 MHz (5) 13 65 mA (6) Power Down Mode 3 10075 m AVCC e 22V to 55V RRST Internal Reset Pulldown Resistor 50 300 KX CIO Pin Capacitance 10 pF NOTES 1 ‘‘Typicals’’ are based on a limited number of samples taken from early manufacturing lots and are not guaranteed The values listed are at room temp 5V 2 Capacitive loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLs of ALE and Ports 1 and 3 The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1- to-0 transitions during bus operations In the worst cases (capacitive loading l 100pF) the noise pulse on the ALE pin may exceed 08V In such cases it may be desirable to qualify ALE with a Schmitt Trigger or use an address latch with a Schmitt Trigger STROBE input 3 Capacitive loading on Ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 09 VCC specification when the address bits are stabilizing 8 |
同様の部品番号 - TP7C31BH |
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同様の説明 - TP7C31BH |
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