Data Sheet

AD5380

TIMING CHARACTERISTICS

SERIAL INTERFACE

unless otherwise noted.

Table 4.

Parameter1, 2, 3

Unit

Description

33

ns min

SCLK cycle time

13

ns min

SCLK high time

13

ns min

SCLK low time

13

ns min

SYNC falling edge to SCLK falling edge setup time

13

ns min

t64

33

ns min

Minimum SYNC low time

10

ns min

Minimum SYNC high time

140

ns min

Minimum SYNC high time in readback mode

5

ns min

Data setup time

4.5

ns min

Data hold time

t104

36

ns max

24th SCLK falling edge to BUSY falling edge

670

ns max

BUSY pulse width low (single channel update)

t124

20

ns min

24th SCLK falling edge to LDAC falling edge

20

ns min

LDAC pulse width low

100/2000

ns min/max

BUSY rising edge to DAC output response time

0

ns min

BUSY rising edge to LDAC falling edge

100/2000

ns min/max

LDAC falling edge to DAC output response time

3

µs typ

DAC output settling time; boost mode off

20

ns min

CLR pulse width low

40

µs max

CLR pulse activation time

30

ns max

SCLK rising edge to SDO valid

t215

5

ns min

SCLK falling edge to SYNC rising edge

t225

8

ns min

SYNC rising edge to SCLK rising edge

20

ns min

SYNC rising edge to LDAC falling edge

1

Guaranteed by design and characterization, not production tested.

2

All input signals are specified with tr = tf = 5 ns (10% to 90% of VCC), and are timed from a voltage level of 1.2 V.

3

See Figure 2, Figure 3, Figure 4, and Figure 5.

4

Standalone mode only.

5

Daisy-chain mode only.

Figure 2. Load Circuit for Digital Output Timing

50pF

TO OUTPUT PIN

200

µA

200

µA

Rev. D | Page 9 of 40