TL16C752B-EP

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SGLS153B – FEBRUARY 2003 – REVISED DECEMBER 2007

FUNCTIONAL DESCRIPTION

The TL16C752B UART is pin-compatible with the ST16C2550 UART. It provides more enhanced features. All

additional features are provided through a special enhanced feature register.

The UART performs a serial-to-parallel conversion on data characters received from peripheral devices or

modems and parallel-to-parallel conversion on data characters transmitted by the processor. The complete

status of each channel of the TL16C752B UART can be read at any time during functional operation by the

processor.

The TL16C752B can be placed in an alternate mode (FIFO mode) relieving the processor of excessive software

overhead by buffering received/transmitted characters. Both the receiver and transmitter FIFOs can store up to

64 bytes (including three additional bits of error status per byte for the receiver FIFO) and have selectable or

programmable trigger levels. Primary outputs RXRDY and TXRDY allow signalling of DMA transfers.

The TL16C752B has selectable hardware flow control and software flow control. Hardware flow control

significantly reduces software overhead and increases system efficiency by automatically controlling serial data

flow using the RTS output and CTS input signals. Software flow control automatically controls data flow by using

programmable Xon/Xoff characters.

The UART includes a programmable baud rate generator that can divide the timing reference clock input by a

Trigger Levels

The TL16C752B provides independent selectable and programmable trigger levels for both receiver and

transmitter DMA and interrupt generation. After reset, both transmitter and receiver FIFOs are disabled and so, in

effect, the trigger level is the default value of one byte. The selectable trigger levels are available via the FCR.

The programmable trigger levels are available via the TLR.

Hardware Flow Control

Hardware flow control is comprised of auto-CTS and auto-RTS. Auto-CTS and auto-RTS can be

enabled/disabled independently by programming EFR[7:6].

With auto-CTS, CTS must be active before the UART can transmit data.

Auto-RTS only activates the RTS output when there is enough room in the FIFO to receive data and deactivates

the RTS output when the RX FIFO is sufficiently full. The halt and resume trigger levels in the TCR determine the

levels at which RTS is activated/deactivated.

If both auto-CTS and auto-RTS are enabled, when RTS is connected to CTS, data transmission does not occur

unless the receiver FIFO has empty space. Thus, overrun errors are eliminated during hardware flow control. If

not enabled, overrun errors occur if the transmit data rate exceeds the receive FIFO servicing latency.

Auto-RTS

Auto-RTS data flow control originates in the receiver block (see functional block diagram). Figure 1 shows RTS

functional timing. The receiver FIFO trigger levels used in auto-RTS are stored in the TCR. RTS is active if the

RX FIFO level is below the halt trigger level in TCR[3:0]. When the receiver FIFO halt trigger level is reached,

RTS is deasserted. The sending device (e.g., another UART) may send an additional byte after the trigger level

is reached (assuming the sending UART has another byte to send), because it may not recognize the

deassertion of RTS until it has begun sending the additional byte. RTS is automatically reasserted once the

receiver FIFO reaches the resume trigger level programmed via TCR[7:4]. This reassertion allows the sending

device to resume transmission.

Copyright © 2003–2007, Texas Instruments Incorporated

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