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CA3130 データシート(PDF) 6 Page - Intersil Corporation

部品番号 CA3130
部品情報  15MHz, BiMOS Operational Amplifier with MOSFET Input/CMOS Output
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メーカー  INTERSIL [Intersil Corporation]
ホームページ  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

CA3130 データシート(HTML) 6 Page - Intersil Corporation

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6
These data show that circuit designers can advantageously
exploit these characteristics to design circuits which typically
require an input current of less than 1pA, provided the
common-mode input voltage does not exceed 2V. As
previously noted, the input current is essentially the result of
the leakage current through the gate-protection diodes in the
input circuit and, therefore, a function of the applied voltage.
Although the finite resistance of the glass terminal-to-case
insulator of the metal can package also contributes an
increment of leakage current, there are useful compensating
factors. Because the gate-protection network functions as if it
is connected to Terminal 4 potential, and the Metal Can case
of the CA3130 is also internally tied to Terminal 4, input
Terminal 3 is essentially “guarded” from spurious leakage
currents.
Offset Nulling
Offset-voltage nulling is usually accomplished with a
100,000
Ω potentiometer connected across Terminals 1 and
5 and with the potentiometer slider arm connected to
Terminal 4. A fine offset-null adjustment usually can be
effected with the slider arm positioned in the mid-point of the
potentiometer’s total range.
Input-Current Variation with Temperature
The input current of the CA3130 Series circuits is typically
5pA at 25oC. The major portion of this input current is due to
leakage current through the gate-protective diodes in the input
circuit. As with any semiconductor-junction device, including
op amps with a junction-FET input stage, the leakage current
approximately doubles for every 10oC increase in
temperature. Figure 4 provides data on the typical variation of
input bias current as a function of temperature in the CA3130.
In applications requiring the lowest practical input current
and incremental increases in current because of “warm-up”
effects, it is suggested that an appropriate heat sink be used
with the CA3130. In addition, when “sinking” or “sourcing”
significant output current the chip temperature increases,
causing an increase in the input current. In such cases, heat-
sinking can also very markedly reduce and stabilize input
current variations.
Input Offset Voltage (VIO) Variation with DC Bias
and Device Operating Life
It is well known that the characteristics of a MOSFET device
can change slightly when a DC gate-source bias potential is
applied to the device for extended time periods. The
magnitude of the change is increased at high temperatures.
Users of the CA3130 should be alert to the possible impacts
of this effect if the application of the device involves
extended operation at high temperatures with a significant
differential DC bias voltage applied across Terminals 2 and
3. Figure 5 shows typical data pertinent to shifts in offset
voltage encountered with CA3130 devices (metal can
package) during life testing. At lower temperatures (metal
can and plastic), for example at 85oC, this change in voltage
is considerably less. In typical linear applications where the
differential voltage is small and symmetrical, these
incremental changes are of about the same magnitude as
those encountered in an operational amplifier employing a
bipolar transistor input stage. The 2VDC differential voltage
example represents conditions when the amplifier output
stage is “toggled”, e.g., as in comparator applications.
10
7.5
5
2.5
0
-1
01234567
INPUT CURRENT (pA)
TA = 25
oC
3
2
7
4
8
6
PA
VIN
CA3130
15V
TO
5V
0V
TO
-10V
V+
V-
FIGURE 3. INPUT CURRENT vs COMMON-MODE VOLTAGE
VS = ±7.5V
4000
1000
100
10
1
-80
-60
-40
-20
0
20
40
60
80
100 120 140
TEMPERATURE (oC)
FIGURE 4. INPUT CURRENT vs TEMPERATURE
CA3130, CA3130A


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