5

bus from the biasing circuit shown in the right hand portion of

geometries are appropriately scaled to provide the requisite

Operating Considerations

Input Circuit

The use of MOS transistors in the input stage of the CA3290

series circuits provides the user with the following features

for comparator applications:

1. Ultra high input impedance (

≅1.7TΩ);

2. The availability of common mode rejection for input signals

at potentials below that of the negative power supply rail;

3. Retention of the in phase relationship of the input and out-

put signals for input signals below the negative rail.

Although the CA3290 employs rugged bipolar (zener) diodes

for protection of the input circuit, the input terminal currents

should not exceed 1mA. Appropriate series connected

limiting resistors should be used in circuits where greater

current flows might exist, allowing the signal input voltage to

be greater than the supply voltage without damaging the

circuit.

Output Circuit

The output of the CA3290 is the open collector of an n-p-n

transistor, a feature providing flexibility in a broad range of

comparator applications. An output ORing function can be

implemented by parallel connection of the open collectors.

An output pull-up resistor can be connected to a power

supply having a voltage range within the rating of the

particular CA3290 in use; the magnitude of this voltage may

be set at a value which is independent of that applied to the

V+ terminal of the CA3290.

Parasitic Oscillations

The ideal comparator has, among other features, ultra high

input impedance, high gain, and wide bandwidth. These

desirable characteristics may, however, produce parasitic

oscillations unless certain precautions are observed to

minimize the stray capacitive coupling between the input and

output terminals. Parasitic oscillations manifest themselves

during the output voltage transition intervals as the

comparator switches states. For high source impedances,

stray capacitance can induce parasitic oscillations. The

addition of a small amount (1mV to 10mV) of positive

feedback (hysteresis) produces a faster transition, thereby

reducing the likelihood of parasitic oscillations. Furthermore,

if the input signal is a pulse waveform, with relatively rapid

rise and fall times, parasitic tendencies are reduced.

When dual comparators, like the CA3290, are packaged in an

8 lead configuration, the output terminal of each comparator is

adjacent to an input terminal. The lead-to-lead capacitance is

approximately 1pF, which may be sufficient to cause

undesirable feedback effects in certain applications. Circuit

factors such as impedance levels, supply voltage, switching

rate, etc., may increase the possibility of parasitic oscillations.

To minimize this potential oscillatory condition, it is

recommended that for source impedances greater than 1k

Ω a

capacitor (

≥1pF - 2pF) be connected between the appropriate

input terminal and the output terminal. (See Figure 1.)

If either comparator is unused, its input terminals should also

be tied to either the V+ or V- supply rail.

Typical Applications

Light Controlled One-Shot Timer

sense a change in photo diode current. The other

switch to a low state for approximately 60 seconds after the

light source to the photo diode has been interrupted. The

circuit operates at normal room lighting levels. The

sensitivity of the circuit may be adjusted by changing the

constant to insure constant reverse voltage bias on the

photo diode.

V+

50

µA

100

µA

50

µA

100

µA

V-

FIGURE 4. BASIC CIRCUIT DIAGRAM FOR ONE OF THE TWO

COMPARATORS

+

-

+15V

7

6

5

+15V

3.3k

Ω

60M

Ω

1.0

µF

10k

Ω

140k

Ω

+

-

1

+15V

1N914

8

4

0.01

µF

1N914

+15V

3

2

1M

Ω

+15V

15k

Ω

1.5M

Ω

2M

Ω

15

k

Ω

C30809

X 60s TIME

FIGURE 5. LIGHT CONTROLLED ONE-SHOT TIMER

CA3290, CA3290A