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CA3304M データシート(PDF) 9 Page - Intersil Corporation

部品番号 CA3304M
部品情報  4-Bit, 25 MSPS, Flash A/D Converters
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メーカー  INTERSIL [Intersil Corporation]
ホームページ  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

CA3304M データシート(HTML) 9 Page - Intersil Corporation

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Description
Device Operation
A sequential parallel technique is used by the CA3304
converter to obtain its high speed operation. The sequence
consists of the “Auto Balance” phase and the “Sample
Unknown” phase (Refer to the circuit diagram). Each
conversion takes one clock cycle (see Note). The “Auto
Balance” (
φ1) occurs during the Low period of the clock
cycle, and the “Sample Unknown” (
φ2) occurs during the
High period of the clock cycle.
NOTE: This device requires only a single-phase clock. The terminology
of
φ1 and φ2 refers to the High and Low periods of the same clock.
During the “Auto Balance” phase, a transmission-gate switch
is used to connect each of 16 commutating capacitors to
their associated ladder reference tap. Those tap voltages will
be as follows:
VTAP(N) = [(VREF/16) x N] - [VREF/(2 x 16)]
= VREF [(2N - 1)/32],
Where:
VTAP(N) = Reference ladder tap voltage at point N,
VREF = Voltage across VREF- to VREF+, and
N = Tap number (1 through 16).
The other side of the capacitor is connected to a single-
stage inverting amplifier whose output is shorted to its input
by a switch. This biases the amplifier at its intrinsic trip point,
which is approximately (VDD - VSS)/2. The capacitors now
charge to their associated tap voltages, priming the circuit for
the next phase.
In the “Sample Unknown” phase, all ladder tap switches are
opened, the comparator amplifiers are no longer shorted,
and VIN is switched to all 16 capacitors. Since the other end
of the capacitor is now looking into an effectively open cir-
cuit, any voltage that differs from the previous tap voltage will
appear as a voltage shift at the comparator amplifiers. All
comparators whose tap voltages were lower than VIN will
drive the comparator outputs to a “low” state. All compara-
tors whose tap voltages were higher than VIN will drive the
comparator outputs to a “high” state. A second, capacitor-
coupled, auto-zeroed amplifier further amplifies the outputs.
The status of all these comparator amplifiers are stored at the
end of this phase (
φ2), by a secondary latching amplifier stage.
Once latched, the status of the 16 comparators is decoded by
a 16 to 5 bit decode array and the results are clocked into a
storage register at the rising edge of the next
φ2.
If the input is greater than 31/32 x VREF, the overflow output
will go “high”. (The bit outputs will remain high). If the output
differs from that of the previous conversion, the data change
output will go “high”.
A three-state buffer is used at the output of the 7 storage
registers which are controlled by two chip-enable signals.
CE1 will independently disable B1 through B4 when it is in a
high state. CE2 will independently disable B1 through B4
and the OF and DC buffers when it is in the low state.
Continuous Clock Operation
One complete conversion cycle can be traced through the
CA3304 via the following steps. (Refer to timing diagram
Figure 3). The rising edge of the clock input will start a
“sample” phase. During this entire “High” state of the clock,
the 16 comparators will track the input voltage and the 16
latches will track the comparator outputs. At the falling edge
of the clock, all 16 comparator outputs are captured by the
16 latches. This ends the “sample” phase and starts the
“auto balance” phase for the comparators. During this “Low”
state of the clock the output of the latches propagates
through the decode array and a 6-bit code appears at the D
inputs of the output registers. On the next rising edge of the
clock, this 6-bit code is shifted into the output registers and
appears with time delay tD as valid data at the output of the
three-state drivers. This also marks the start of a new
“sample” phase, thereby repeating the conversion process
for this next cycle.
Pulse Mode Operation
For sampling high speed nonrecurrent or transient data, the
converter may be operated in a pulse mode in one of three
ways. The fastest method is to keep the converter in the
Sample Unknown phase,
φ2, during the standby state. The
device can now be pulsed through the Auto Balance phase
with as little as 20ns. The analog value is captured on the
leading edge of
φ1 and is transferred into the output registers
on the trailing edge of
φ1. We are now back in the standby
state,
φ2, and another conversion can be started within
20ns, but not later than 5
µs due to the eventual droop of the
commutating capacitors. Another advantage of this method
is that it has the potential of having the lowest power drain.
The larger the time ratio between
φ2 and φ1, the lower the
power consumption. (See Timing Diagram Figure 3A).
The second method uses the Auto Balance phase,
φ1, as
the standby state. In this state the converter can stay
indefinitely waiting to start a conversion. A conversion is
performed by strobing the clock input with two
φ2 pulses.
The first pulse starts a Sample Unknown phase and
captures the analog value in the comparator latches on the
trailing edge. A second
φ2 pulse is needed to transfer the
date into the output registers. This occurs on the leading
edge of the second pulse. The conversion now takes place
in 40ns, but the repetition rate may be as slow as desired.
The disadvantage to this method is the slightly higher device
dissipation due to the low ratio of
φ2 to φ1. (See Timing
Diagram Figure 3B).
For applications requiring both indefinite standby and lowest
power, standby can be in the
φ2 (Sample Unknown) state
with two
φ1 pulses to generate valid data (see Figure 3C).
The conversion process now takes 60ns. [Note that the
above numbers do not include the tD (Output Delay) time.]
Increased Accuracy
In most case the accuracy of the CA3304 should be
sufficient without any adjustments. In applications where
accuracy is of utmost importance, two adjustments can be
made to obtain better accuracy; i.e., offset trim and gain trim.
CA3304, CA3304A


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