10-15

Latch Operation

Data is fed from input to output while LE is low: LE should be

tied low for non-clocked operation.

Non-clocked operation or changing data while LE is low is

not recommended for applications requiring low output

“glitch” energy: there is no guarantee of the simultaneous

changing of input data or the equal propagation delay of all

bits through the converter. Several parameters are given if

gives the delay from the input changing to the output chang-

(referred to LE rising edge) needed to latch data. See

Figures 1 and 2.

Clocked operation is needed for low “glitch” energy use.

falling edge.

There is no need for a square wave LE clock; LE must only

tion. Generally, output timing (desired accuracy of settling)

sets the upper limit of usable clock frequency.

Output Structure

The latches feed data to a row of high current CMOS drivers,

which in turn feed a modified R2R ladder network.

The “N” channel (pull down) transistor of each driver plus the

scale reference. The “P” channel (pull up) transistor of each

analog ground, but may be raised above ground (see specifi-

cations). There is substantial code dependent current that

to ground.

output drivers, must be returned to a point at least as nega-

decreases when the bipolar mode is used.

Static Characteristics

code of FFHEX (full scale output). The difference between the

ideal and actual values of these two parameters are the OFF-

SET and GAIN errors, respectively; see Figure 3.

If the code into an 8-bit D/A is changed by 1 count, the output

should change by 1/255 (full scale output - zero scale output). A

deviation from this step size is a differential linearity error, see

Figure 4. Note that the error is expressed in fractions of the

ideal step size (usually called an LSB). Also note that if the (-)

differential linearity error is less (in absolute numbers) than 1

LSB, the device is monotonic. (The output will always increase

for increasing code or decrease for decreasing code).

If the code into an 8-bit D/A is at any value, say “N”, the output

voltage should be N/255 of the full scale output (referred to the

zero scale output). Any deviation from that output is an integral

linearity error, usually expressed in LSBs. See Figure 4.

Note that OFFSET and GAIN errors do not affect integral

linearity, as the linearity is referenced to actual zero and full

scale outputs, not ideal. Absolute accuracy would have to

also take these errors into account.

INPUT DATA

LATCH

ENABLE

LATCHED

LATCHED

DATA

FEEDTHROUGH

FIGURE 1. DATA TO LATCH ENABLE TIMING

90%

10%

INPUT

LATCH

ENABLE

OUTPUT

VOLTAGE

DATA

FIGURE 2. DATA AND LATCH ENABLE TO OUTPUT TIMING

255/256

254/256

253/256

3/256

2/256

1/256

0

00

01

02

03

FD

FE

FF

= IDEAL TRANSFER CURVE

= ACTUAL TRANSFER CURVE

OFFSET

ERROR

(SHOWN +)

GAIN ERROR

(SHOWN -)

INPUT CODE IN HEXADECIMAL (COMP = LOW)

FIGURE 3. D/A OFFSET AND GAIN ERROR

CA3338, CA3338A