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CA5160M96 データシート(PDF) 5 Page - Intersil Corporation

部品番号 CA5160M96
部品情報  4MHz, BiMOS Microprocessor Operational Amplifiers with MOSFET Input/CMOS Output
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メーカー  INTERSIL [Intersil Corporation]
ホームページ  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

CA5160M96 データシート(HTML) 5 Page - Intersil Corporation

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3-5
Schematic Diagram
Application Information
Circuit Description
Refer to the block diagram of the CA5160 CMOS Operational
Amplifier. The input terminals may be operated down to 0.5V
below the negative supply rail, and the output can be swung
very close to either supply rail in many applications. Conse-
quently, the CA5160 circuit is ideal for single supply operation.
Three class A amplifier stages, having the individual gain
capability and current consumption shown in the block dia-
gram, provide the total gain of the CA5160. A biasing circuit
provides two potentials for common use in the first and sec-
ond stages. Terminals 8 and 1 can be used to supplement the
internal phase compensation network if additional phase com-
pensation or frequency roll-off is desired. Terminals 8 and 4
can also be used to strobe the output stage into a low quies-
cent current state. When Terminal 8 is tied to the negative
supply rail (Terminal 4) by mechanical or electrical means, the
output potential at Terminal 6 essentially rises to the positive
supply rail potential at Terminal 7. This condition of essentially
zero current drain in the output stage under the strobed “OFF”
condition can only be achieved when the ohmic load resis-
tance presented to the amplifier is very high (e.g., when the
amplifier output is used to drive CMOS digital circuits in com-
parator applications).
Input Stages
The circuit of the CA5160 is shown in the schematic diagram.
It consists of a differential input stage using PMOS field effect
transistors (Q6, Q7) working into a mirror pair of bipolar tran-
sistors (Q9, Q10) functioning as load resistors together with
resistors R3 through R6. The mirror pair transistors also func-
tion as a differential-to-single-ended converter to provide base
drive to the second-stage bipolar transistor (Q11). Offset null-
ing, when desired, can be effected by connecting a 100,000
potentiometer across Terminals 1 and 5 and the potentiome-
ter slider arm to Terminal 4.
Cascode-connected PMOS transistors Q2, Q4, are the
constant current source for the input stage. The biasing
circuit for the constant current source is subsequently
described. The small diodes D5 through D7 provide gate-
oxide protection against high voltage transients, including
static electricity during handling for Q6 and Q7.
Second Stage
Most of the voltage gain in the CA5160 is provided by the
second amplifier stage, consisting of bipolar transistor Q11
and its cascode-connected load resistance provided by
7
4
8
1
5
2
3
BIAS CIRCUIT
“CURRENT SOURCE
LOAD” FOR Q11
Q2
D1
D2
D3
D4
Z1
8.3V
Q1
R1
40k
Q4
R2
5k
INPUT STAGE
D5
NON-INV.
INPUT
INV. INPUT
+
-
Q6
R3
1k
Q9
Q10
R5
1k
R6
1k
R4
1k
Q7
D6
D7
Q3
OFFSET NULL
Q11
SUPPLEMENTARY
COMP IF DESIRED
STROBING
SECOND
OUTPUT
Q8
Q12
STAGE
STAGE
Q5
V+
2k
30
pF
6
OUTPUT
CURRENT SOURCE
FOR Q6 AND Q7
NOTE: Diodes D5 through D7 provide gate oxide protection for MOSFET Input Stage.
CA5160


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