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CD40101BMS データシート(PDF) 1 Page - Intersil Corporation

部品番号 CD40101BMS
部品情報  CMOS 9-Bit Parity Generator/Checker
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メーカー  INTERSIL [Intersil Corporation]
ホームページ  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

CD40101BMS データシート(HTML) 1 Page - Intersil Corporation

  CD40101BMS Datasheet HTML 1Page - Intersil Corporation CD40101BMS Datasheet HTML 2Page - Intersil Corporation CD40101BMS Datasheet HTML 3Page - Intersil Corporation CD40101BMS Datasheet HTML 4Page - Intersil Corporation CD40101BMS Datasheet HTML 5Page - Intersil Corporation CD40101BMS Datasheet HTML 6Page - Intersil Corporation CD40101BMS Datasheet HTML 7Page - Intersil Corporation CD40101BMS Datasheet HTML 8Page - Intersil Corporation  
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
CD40101BMS
CMOS 9-Bit Parity Generator/Checker
Features
• High Voltage Type (20V Rating)
• 100% Tested for Quiescent Current at 20V
• 5V, 10V and 15V Parametric Ratings
• Maximum Input Current of 1
µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25oC
• Noise Margin (Over Full Package/Temperature Range)
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• Standardized Symmetrical Output Characteristics
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
Description
The CD40101BMS is a 9-bit (8 data bits plus 1 parity bit)
parity generator/checker. It may be used to detect errors in
data transmission or data retrieval. Odd and even outputs
facilitate odd or even parity generation and checking.
When used as a parity generator, a parity bit is supplied
along with the data to generate an even or odd parity output.
When used as a parity checker, the received data bits and
parity bits are compared for correct parity. The even or odd
outputs are used to indicate an error in the received data.
Word length capability is expandable by cascading. The
CD40101BMS is also provided with an inhibit control. If the
inhibit control is set at logical “1”, the even and odd outputs
go to a logical “0”.
The CD40101BMS is supplied in these 14 lead outline
packages:
Braze Seal DIP
H4H
Frit Seal DIP
H1B
Ceramic Flatpack
H3W
December 1992
File Number
3350
Pinout
CD40101BMS
TOP VIEW
Functional Diagram
D1
D2
D3
D4
D9
ODD OUT
VSS
VDD
D8
D7
D6
D5
EVEN OUT
INHIBIT
1
2
3
4
5
6
7
14
13
12
11
10
9
8
DECODE
INHIBIT
8
D1
1
2
3
4
10
11
12
13
5
D2
D3
D4
D5
D6
D7
D8
D9
EVEN
OUTPUT
9
ODD
OUTPUT
6
VDD = 14
VSS = 7


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