7-1302

CD40102BMS, CD40103BMS

TRUTH TABLE

CONTROL INPUTS

PRESET MODE

ACTION

CLR

APE

SPE

CI/CE

1

1

1

1

Synchronous

Inhibit Counter

1

1

1

0

Count Down*

1

1

0

X

Preset on next positive clock transition

1

0

X

X

Asynchronous

Preset Asynchronously

0

X

X

X

Clear to maximum count

NOTES:

1. 0 = Low Level

1 = High Level

X = Don’t Care

2. Clock connected to clock input

3. Synchronous operation: changes occur on negative-to-posi-

tive clock transitions

4. JAM inputs: CD40102BMS;

MSD = J7, J6, J5, J4, (J7 is MSB)

LSD = J3, J2, J1, J0 (J3 is MSB)

CD40103BMS Binary;

MBS = J7, LSB = J0

*At zero count, the counters will jump to the maximum count on the next clock transition to “High”

Typical Performance Characteristics

FIGURE 3. TYPICAL OUTPUT LOW (SINK) CURRENT

CHARACTERISTICS

FIGURE 4. MINIMUM OUTPUT LOW (SINK) CURRENT

CHARACTERISTICS

FIGURE 5. TYPICAL OUTPUT HIGH (SOURCE) CURRENT

CHARACTERISTICS

FIGURE 6. MINIMUM OUTPUT HIGH (SOURCE) CURRENT

CHARACTERISTICS

10V

5V

GATE-TO-SOURCE VOLTAGE (VGS) = 15V

0

5

10

15

15

10

5

20

25

30

DRAIN-TO-SOURCE VOLTAGE (VDS) (V)

10V

5V

GATE-TO-SOURCE VOLTAGE (VGS) = 15V

0

5

10

15

7.5

5.0

2.5

10.0

12.5

15.0

DRAIN-TO-SOURCE VOLTAGE (VDS) (V)

-10V

-15V

GATE-TO-SOURCE VOLTAGE (VGS) = -5V

0

-5

-10

-15

DRAIN-TO-SOURCE VOLTAGE (VDS) (V)

-20

-25

-30

0

-5

-10

-15

-10V

-15V

0

-5

-10

-15

DRAIN-TO-SOURCE VOLTAGE (VDS) (V)

0

-5

-10

-15

GATE-TO-SOURCE VOLTAGE (VGS) = -5V