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AD9949 データシート(PDF) 5 Page - Analog Devices |
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AD9949 データシート(HTML) 5 Page - Analog Devices |
5 / 36 page AD9949 Rev. B | Page 5 of 36 TIMING SPECIFICATIONS CL = 20 pF, fCLI = 36 MHz, unless otherwise noted. Table 4. Parameter Symbol Min Typ Max Unit MASTER CLOCK (CLI) (See Figure 16) CLI Clock Period tCLI 27.8 ns CLI High/Low Pulse Width tADC 11.2 13.9 16.6 ns Delay from CLI to Internal Pixel Period Position tCLIDLY 6 ns CLPOB PULSE WIDTH (PROGRAMMABLE)1 tCOB 2 20 Pixels SAMPLE CLOCKS (See Figure 18) SHP Rising Edge to SHD Rising Edge tS1 12.5 13.9 ns DATA OUTPUTS (See Figure 19 and Figure 20) Output Delay From Programmed Edge tOD 6 ns Pipeline Delay 11 Cycles SERIAL INTERFACE (SERIAL TIMING SHOWN IN Figure 14 and Figure 15) Maximum SCK Frequency fSCLK 10 MHz SL to SCK Setup Time tLS 10 ns SCK to SL Hold Time tLH 10 ns SDATA Valid to SCK Rising Edge Setup tDS 10 ns SCK Falling Edge to SDATA Valid Hold tDH 10 ns SCK Falling Edge to SDATA Valid Read tDV 10 ns 1 Minimum CLPOB pulse width is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp reference. |
同様の部品番号 - AD9949_15 |
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同様の説明 - AD9949_15 |
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