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AD9983A データシート(PDF) 11 Page - Analog Devices |
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AD9983A データシート(HTML) 11 Page - Analog Devices |
11 / 44 page AD9983A Rev. 0 | Page 11 of 44 In most PC graphics systems, black is transmitted between active video lines. With CRT displays, when the electron beam has completed writing a horizontal line on the screen (at the right side), the beam is deflected quickly to the left side of the screen (called horizontal retrace) and a black signal is provided to prevent the beam from disturbing the image. In systems with embedded sync, a blacker-than-black signal (Hsync) is produced briefly to signal the CRT that it is time to begin a retrace. Because the input is not at black level at this time, it is important to avoid clamping during Hsync. Fortu- nately, there is usually a period following Hsync, called the back porch, where a good black reference is provided. This is the time when clamping should be done. The clamp timing can be established by simply exercising the CLAMP pin at the appropriate time with clamp source (Register 0x18, Bit 4) = 1. The polarity of this signal is set by the clamp polarity bit, (Register 0x1B, Bits[7:6]). A simpler method of clamp timing employs the AD9983A internal clamp timing generator. The clamp placement register (Register 0x19) is programmed with the number of pixel periods that should pass after the trailing edge of Hsync before clamping starts. A second register, clamp duration, (Register 0x1A) sets the duration of the clamp. These are both 8-bit values, providing considerable flexibility in clamp generation. The clamp timing is referenced to the trailing edge of Hsync because, though Hsync duration can vary widely, the back porch (black reference) always follows Hsync. A good starting point for establishing clamping is to set the clamp placement to 0x04 (providing 4 pixel periods for the graphics signal to stabilize after sync) and set the clamp duration to 0x28 (giving the clamp 40 pixel periods to reestablish the black reference). Clamping is accomplished by placing an appropriate charge on the external input coupling capacitor. The value of this capacitor affects the performance of the clamp. If it is too small, there will be a significant amplitude change during a horizontal line time (between clamping intervals). If the capacitor is too large, it will take too long for the clamp to recover from a large change in incoming signal offset. The recommended value (47 nF) results in recovering from a step error of 100 mV to within 1 LSB in 30 lines with a clamp duration of 20 pixel periods on a 85 Hz XGA signal. YPbPr Clamping YPbPr graphic signals are slightly different from RGB signals in that the dc reference level (black level in RGB signals) of color difference signals is at the midpoint of the video signal rather than at the bottom. The three inputs are composed of luminance (Y) and color difference (Pb and Pr) signals. For color difference signals, it is necessary to clamp to the midscale range of the ADC range (512) rather than to the bottom of the ADC range (0), while the Y channel is clamped to ground. Clamping to midscale rather than ground can be accomplished by setting the clamp select bits in the serial bus register. Each of the three converters has its own selection bit so that they can be clamped to either midscale or ground independently. These bits are located in Register 0x18, Bits[3:1]. The midscale reference voltage is internally generated for each converter. GAIN AND OFFSET CONTROL The AD9983A contains three PGAs, one for each of the three analog inputs. The range of the PGA is sufficient to accom- modate input signals with inputs ranging from 0.5 V to 1.0 V full scale. The gain is set in three 7-bit registers (red gain [0x05], green gain [0x07], blue gain [0x09]). For each register, a gain setting of 0 corresponds to the highest gain, while a gain setting of 127 corresponds to the lowest gain. Note that increasing the gain setting results in an image with less contrast. The offset control shifts the analog input, resulting in a change in brightness. Three 9-bit registers red offset [Register 0x0B and Register 0x0C], green offset [Register 0x0D and Register 0x0E], and blue offset [Register 0x0F and Register 0x10] provide independent settings for each channel. Note that the function of the offset register depends on whether auto-offset is enabled (Register 0x1B, Bit 5). If manual offset is used, seven bits of the offset registers (for the red channel Register 0x0B, Bits[6:0]) control the absolute offset added to the channel. The offset control provides ±63 LSBs of adjustment range, with 1 LSB of offset corresponding to 1 LSB of output code. Automatic Offset In addition to the manual offset adjustment mode, the AD9983A also includes circuitry to automatically calibrate the offset for each channel. By monitoring the output of each ADC during the back porch of the input signals, the AD9983A can self-adjust to eliminate any offset errors in its own ADC channels and any offset errors present on the incoming graphics or video signals. To activate the auto-offset mode, set Register 0x1B, Bit 5 to 1. Next, the target code registers (Register 0x0B through Register 0x10) must be programmed. The values programmed into the target code registers should be the output code desired from the AD9983A ADCs, which are generated during the back porch reference time. For example, for RGB signals, all three registers are normally programmed to Code 2, while for YPbPr signals the green (Y) channel is normally programmed to Code 2 and the blue and red channels (Pb and Pr) are normally set to 128. The target code registers have nine bits per channel and are in twos complement format. This allows any value between –256 and +255 to be programmed. Although any value in this range can be programmed, the AD9983A offset range may not be able to reach every value. Intended target code values range from (but are not limited to) –40 to –1 and 1 to 40 when ground clamping and 88 to 168 when midscale clamping. Note that a target code of 0 is not valid. |
同様の部品番号 - AD9983A_15 |
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同様の説明 - AD9983A_15 |
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