ADM1064_15 datasheet(5/32 Pages) AD

部品番号	ADM1064

部品情報	Super Sequencer with Voltage Readback ADC

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ADM1064

Rev. D | Page 5 of 32

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

Conversion Time

0.44

ms

One conversion on one channel

84

ms

All 12 channels selected, averaging enabled

Offset Error

±2

LSB

VREFIN = 2.048 V

Input Noise

0.25

LSB rms

Direct input (no attenuator)

REFERENCE OUTPUT

Reference Output Voltage

2.043

2.048

2.053

V

No load

Load Regulation

−0.25

mV

Sourcing current

0.25

mV

Sinking current

Minimum Load Capacitance

1

μF

Capacitor required for decoupling, stability

PSRR

60

dB

DC

PROGRAMMABLE DRIVER OUTPUTS

High Voltage (Charge Pump) Mode

(PDO1 to PDO6)

Output Impedance

500

kΩ

VOH

11

12.5

14

V

IOH = 0 μA

10.5

12

13.5

V

IOH = 1 μA

IOUTAVG

20

μA

2 V < VOH < 7 V

Standard (Digital Output) Mode

(PDO1 to PDO10)

VOH

2.4

V

VPU (pull-up to VDDCAP or VPx) = 2.7 V, IOH = 0.5 mA

4.5

V

VPU to VPx = 6.0 V, IOH = 0 mA

VPU − 0.3

V

VPU ≤ 2.7 V, IOH = 0.5 mA

VOL

0

0.50

V

IOL = 20 mA

IOL2

20

mA

Maximum sink current per PDOx pin

ISINK2

60

mA

Maximum total sink for all PDOx pins

RPULL-UP

16

20

29

kΩ

Internal pull-up

ISOURCE (VPx)2

2

mA

Current load on any VPx pull-ups, that is, total source

current available through any number of PDOx pull-up

switches configured onto any one VPx pin

Three-State Output Leakage Current

10

μA

VPDO = 14.4 V

Oscillator Frequency

90

100

110

kHz

All on-chip time delays derived from this clock

DIGITAL INPUTS (VXx, A0, A1)

Input High Voltage, VIH

2.0

V

Maximum VIN = 5.5 V

Input Low Voltage, VIL

0.8

V

Maximum VIN = 5.5 V

Input High Current, IIH

−1

μA

VIN = 5.5 V

Input Low Current, IIL

1

μA

VIN = 0

Input Capacitance

5

pF

Programmable Pull-Down Current, IPULL-DOWN

20

μA

VDDCAP = 4.75 V, TA = 25°C, if known logic state is

required

SERIAL BUS DIGITAL INPUTS (SDA, SCL)

Input High Voltage, VIH

2.0

V

Input Low Voltage, VIL

0.8

V

Output Low Voltage, VOL2

0.4

V

IOUT = −3.0 mA

SERIAL BUS TIMING3

Clock Frequency, fSCLK

400

kHz

Bus Free Time, tBUF

1.3

μs

Start Setup Time, tSU;STA

0.6

μs

Stop Setup Time, tSU;STO

0.6

μs

Start Hold Time, tHD;STA

0.6

μs

SCL Low Time, tLOW

1.3

μs

SCL High Time, tHIGH

0.6

μs

SCL, SDA Rise Time, tR

300

ns

SCL, SDA Fall Time, tF

300

ns

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同様の説明 - ADM1064_15

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