データシートサーチシステム |
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ADV7343 データシート(PDF) 10 Page - Analog Devices |
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ADV7343 データシート(HTML) 10 Page - Analog Devices |
10 / 108 page ADV7342/ADV7343 Data Sheet Rev. | Page 10 of 108 DIGITAL TIMING SPECIFICATIONS—1.8 V VDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, VAA = 2.6 V to 3.465 V, VDD_IO = 1.71 V to 1.89 V. All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted. Table 9. Parameter Conditions1 Min Typ Max Unit VIDEO DATA AND VIDEO CONTROL PORT2, 3 Data Input Setup Time, t114 SD 1.4 ns ED/HD-SDR 1.9 ns ED/HD-DDR 1.9 ns ED (at 54 MHz) 1.6 ns Data Input Hold Time, t124 SD 1.4 ns ED/HD-SDR 1.5 ns ED/HD-DDR 1.5 ns ED (at 54 MHz) 1.3 ns Control Input Setup Time, t114 SD 1.4 ns ED/HD-SDR or ED/HD-DDR 1.2 ns ED (at 54 MHz) 1.0 ns Control Input Hold Time, t124 SD 1.4 ns ED/HD-SDR or ED/HD-DDR 1.0 ns ED (at 54 MHz) 1.0 ns Control Output Access Time, t134 SD 13 ns ED/HD-SDR, ED/HD-DDR or ED (at 54 MHz) 12 ns Control Output Hold Time, t144 SD 4.0 ns ED/HD-SDR, ED/HD-DDR or ED (at 54 MHz) 5.0 ns PIPELINE DELAY5 SD1 CVBS/YC Outputs (2×) SD oversampling disabled 68 Clock cycles CVBS/YC Outputs (16×) SD oversampling enabled 67 Clock cycles Component Outputs (2×) SD oversampling disabled 78 Clock cycles Component Outputs (16×) SD oversampling enabled 84 Clock cycles ED1 Component Outputs (1×) ED oversampling disabled 41 Clock cycles Component Outputs (8×) ED oversampling enabled 46 Clock cycles HD1 Component Outputs (1×) HD oversampling disabled 40 Clock cycles Component Outputs (4×) HD oversampling enabled 44 Clock cycles 1 SD = standard definition, ED = enhanced definition (525p/625p), HD = high definition, SDR = single data rate, DDR = dual data rate. 2 Video data: C[7:0], Y[7:0], and S[7:0]. 3 Video control: P_HSYNC, P_VSYNC, P_BLANK, S_HSYNC, and S_VSYNC. 4 Guaranteed by characterization. 5 Guaranteed by design. D |
同様の部品番号 - ADV7343_15 |
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同様の説明 - ADV7343_15 |
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