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J111 データシート(PDF) 1 Page - Calogic, LLC |
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J111 データシート(HTML) 1 Page - Calogic, LLC |
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1 / 1 page N-Channel JFET Switch J111 - J113 / SST111 – SST113 FEATURES •• Low Cost •• Automated Insertion Package •• Low Insertion Loss •• No Offset or Error Voltage Generated By Closed Switch - Purely Resistive - High Isolation Resistance From Driver •• Fast Switching •• Short Sample and Hold Aperture Time APPLICATIONS •• Analog Switches •• Choppers •• Commutators ABSOLUTE MAXIMUM RATINGS (TA = 25 oC unless otherwise specified) Gate-Drain or Gate-Source Voltage . . . . . . . . . . . . . . . . -35V Gate Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA Storage Temperature Range . . . . . . . . . . . . . -55 oC to +150oC Operating Temperature Range . . . . . . . . . . . -55 oC to +135oC Lead Temperature (Soldering, 10sec) . . . . . . . . . . . . . +300 oC Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . 360mW Derate above 25 oC . . . . . . . . . . . . . . . . . . . . . . 3.3mW/oC NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ORDERING INFORMATION Part Package Temperature Range J111-113 Plastic TO-92 -55 oC to +135oC SST111-113 Plastic SOT-23 -55 oC to +135oC For Sorted Chips in Carriers see 2N4391 series. LLC PIN CONFIGURATION 5001 ELECTRICAL CHARACTERISTICS (TA = 25 oC unless otherwise specified) SYMBOL PARAMETER 111 112 113 UNITS TEST CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX IGSSR Gate Reverse Current (Note 1) -1 -1 -1 nA VDS = 0V, VGS = -15V VGS(off) Gate Source Cutoff Voltage -3 -10 -1 -5 -0.5 -3 V VDS = 5V, ID = 1 µA BVGSS Gate Source Breakdown Voltage -35 -35 -35 VDS = 0V, IG = -1 µA IDSS Drain Saturation Current (Note 2) 20 5 2 mA VDS = 15V, VGS = 0V ID(off) Drain Cutoff Current (Note 1) 1 1 1 nA VDS = 5V, VGS = -10V rDS(on) Drain Source ON Resistance 30 50 100 Ω VDS = 0.1V, VGS = 0V Cdg(off) Drain Gate OFF Capacitance 5 5 5 pF VDS = 0, VGS = -10V (Note 3) f = 1MHz Csg(off) Source Gate OFF Capacitance 5 5 5 Cdg(on) + Csg(on) Drain Gate Plus Source Gate ON Capacitance 28 28 28 VDS = VGS = 0 (Note 3) td(on) Turn On Delay Time 7 7 7 ns Switching Time Test Conditions (Note 3) J111 J112 J113 VDD 10V 10V 10V VGS(off) -12V -7V -5V RL 0.8k Ω 1.6kΩ 3.2kΩ tr Rise Time 6 6 6 td(off) Turn Off Delay Time 20 20 20 tf Fall Time 15 15 15 NOTES: 1. Approximately doubles for every 10 oC increase in TA. 2. Pulse test duration 300 µs; duty cycle ≤3%. 3. For design reference only, not 100% tested. SOT-23 G S D TO-92 S G D PRODUCT MARKING (SOT-23) SST111 111 SST112 112 SST113 113 CALOGIC LLC, 237 WHITNEY PLACE, FREMONT, CA 94539. 510-656-2900 PHONE, 510-651-1076 FAX DS039 REV A |
同様の部品番号 - J111_15 |
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同様の説明 - J111_15 |
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