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LF3310QC12 データシート(PDF) 6 Page - LOGIC Devices Incorporated |
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LF3310QC12 データシート(HTML) 6 Page - LOGIC Devices Incorporated |
6 / 21 page DEVICES INCORPORATED LF3310 Horizontal / Vertical Digital Image Filter 6 Video Imaging Products 11/08/2001-LDS.3310-H The HV Filter can handle kernel sizes of 3-3, 5-5, and 7-7 (see Figure 7). Data delay elements at the input of the horizontal filter and the output of the vertical filter are used to properly align data so that the orthogonal kernel is implemented correctly. The data delays are automatically set to the correct lengths based on the programmed length of the line buffers and the kernel size. Kernel sizes of 3-3, 5-5, and 7-7 require that the horizontal filter’s output be delayed by LB – 2, 2(LB) – 3, and 3(LB) – 4 clock cycles respectively before being added to the vertical filter’s output (LB is the programmed line buffer length). The data delay at the input of the horizontal filter handles the LB, 2(LB), and 3(LB) delays. The data delay at the output of the vertical filter handles the – 2, – 3, and – 4 delays. For example, if the line buffers are programmed for a length of 720 and a 5–5 kernel is selected, the horizontal filter input data delay will be 1440 clock cycles and the vertical filter output data delay will be 3 clock cycles. It is important to note that the first 3, 5, or 7 multipliers of the horizontal and vertical filters must be used in Orthogonal Mode. If other multipli- ers are used, data from the horizontal and vertical filters will not line up correctly because the data delays are calculated assuming that the first 3, 5, or 7 multipliers are used. Also, the ALUs in the horizontal filter should be configured to accept data from the forward I/D Register path into ALU Input A and force ALU Input B to 0. FUNCTIONAL DESCRIPTION Horizontal Filter The horizontal filter is designed to filter a digital image in the horizontal dimension. This FIR filter can be configured to have as many as 16-taps when symmetric coefficient sets are used and 8-taps when asymmetric coefficient sets are used. ALUs The ALUs double the number of filter taps available, when symmetric coefficient sets are used, by pre-adding data values which are then multiplied by a common coeffi- cient (see Figure 8). The ALUs can perform two operations: A+B and B–A. Bit 0 of Configuration Regis- ter 0 determines the ALU operation. A+B is used with even-symmetric coefficient sets. B–A is used with odd-symmetric coefficient sets. Also, either the A or B operand may be set to 0. Bits 1 and 2 of Configuration Register 0 control the ALU inputs. A+0 or B+0 are used with asymmetric coefficient sets. Interleave/Decimation Registers The Interleave/Decimation Registers (I/D Registers) feed the ALU inputs. They allow the device to filter up to sixteen data sets interleaved into the same data stream without having to separate the data sets. The I/D Registers should be set to a length equal to the number of data sets interleaved together. For example, if two data sets are interleaved together, the I/D Registers should be set to a length of two. Bits 1 through 4 of Configuration Register 1 determine FIGURE 6. ORTHOGONAL MODE DIN11-0 HORIZONTAL FILTER LINE BUFFER 12 LINE BUFFER LINE BUFFER LINE BUFFER LINE BUFFER LINE BUFFER LINE BUFFER DOUT11-0 12 DATA DELAY DATA DELAY FIGURE 7. 3-3, 5-5, AND 7-7 ORTHOGONAL KERNELS V2 V3 HV4 H3 H5 V5 V6 H2 H6 H1 H7 V1 V7 V1 V2 HV3 H2 H4 V4 V5 H1 H5 V1 HV2 H1 H3 V3 |
同様の部品番号 - LF3310QC12 |
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同様の説明 - LF3310QC12 |
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