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8V44N4614 データシート(PDF) 8 Page - Integrated Device Technology |
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8V44N4614 データシート(HTML) 8 Page - Integrated Device Technology |
8 / 31 page 8V44N4614 DATA SHEET FEMTOCLOCK® NG JITTER ATTENUATOR AND CLOCK SYNTHESIZER 8 REVISION 1 02/25/15 Test Mode: Output Frequency Margining The 8V44N4614 supports a test operation by setting the TEST input to logic high level. In test mode, the PLL allows to vary its center frequency. While the input frequency stays constant, all outputs change its frequency following the PLL frequency variation. The test mode supports 19.53125ppm frequency steps and to a total frequency variation range of ±507.8125ppm. To facilitate this test mode, the fractional PLL feedback divider MT is used. MT consists of an integer part (MINT) and a fractional part (MFRAC). The amount o frequency variation can be configured by the content of the Test Control SPI registers. Table 3K illustrates the available settings. Serial Control Port Description The 8V44N4614 has a serial control port capable of responding as a slave in an SPI configuration to allow read and write access to any of the internal registers (Table 4A) for device programming or read back. The SPI interface consists of the SPICLK (clock), MISO (serial data output), MOSI (serial data input) and nCS (chip select) pins. See Figure 1 for a supported SPI configuration the specific sections for each register for details on meanings and default conditions. SPI Mode Operation During a SPI data transfer, data is shifted out serially from MISO and shifted in serially from MOSI simultaneously. The SPI clock synchronizes both transmitting and receiving of the two serial data pins. A data transfer consists any integer multiple of 32 bits and is always initiated by a SPI master on the bus. If nCS is at logic high, the MISO data output is in high-impedance state and the SPI interface of the 8V44N4614 is disabled. Starting a data transfer requires nCS to set and hold at logic low level during the entire transfer. SPI word (32 bit) and back-to-back transfers of multiple words of 32 bits are supported, during multiple transfers nCS can stay at logic low level. Setting nCS = 0 will enable the MISO output and present the last bit position of the shift register (D31) at that output. The first rising edge of SPICLK will transfer the bit applied to the MOSI input into the first bit, (bit position D0) of the internal shift register and the following SPICLK falling edge will output the next bit of the internal shift register to the MISO output. Each SPICLK cycle will further input one bit to MOSI, shift the content of the shift register by one position and present the last bit to the MISO output. With a total of 32 SPICLK cycles, 32 bit are transferred from the master to the 8V44N4614 slave and also 32 bit are transferred from the slave to the master. During each transfer, the original data content of the internal shift register is replaced by the data shifted in through the MOSI pin. Internal register data is organized in SPI words of 32 bit. The first bit presented by the SPI master in each transfer is the LSB (least significant bit). Write operation to a 8V44N4614 register: During a write transfer, a SPI master transfers one or more words of 32 bits data into the internal registers of the 8V44N4614. A write transfer must set the direction bit R/Wn (D4) to 0 (Write) and D0 to D3 must contain the 4-bit register base address A[0:3]. Bits D5 to 31 contain 27 bit of payload data, which is written into the base register addressed by A[0:3] at the end of the write transfer. The word format of the 32-bit word in the shift register is shown in Table 3L. Each transferred SPI word writes the information to four internal 8-bit registers at once. The 8-bit registers in the 8V44N4614 have been organized so that the 5 address + direction bits in each 32-bit base register row are not used for data transfer (only 27 bits are used). Each base address supports 4 registers at the byte offsets 00, 01, 10 and 11. Table 3K. Test Mode Frequency Variation Output Frequency Variation Absolute Frequency Variation MT (Binary) (ppm) from 100MHz (kHz) from 156.25MHz (kHz) MINT[6:0] MFRAC[8:0] -507.81250 -50.78125 -79.34570 1100011 111100110 -488.28125 -48.82813 -76.29395 1100011 111100111 …. . . …. . . …. . . …. . . …. . . -39.06250 -3.90625 -6.10352 1100011 111111110 -19.53125 -1.95313 -3.05176 1100011 111111111 0.00000 0 0 1100100 000000000 19.53125 1.95313 3.05176 1100100 000000001 39.06250 3.90625 6.10352 1100100 000000010 …. . . …. . . …. . . …. . . …. . . 488.28125 48.82813 76.29395 1100100 000011001 507.81250 50.78125 79.34570 1100100 000011010 |
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同様の説明 - 8V44N4614 |
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