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ISL9305IRTAANLZ-T データシート(PDF) 12 Page - Intersil Corporation |
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ISL9305IRTAANLZ-T データシート(HTML) 12 Page - Intersil Corporation |
12 / 16 page ISL9305 12 FN7605.2 February 9, 2015 Submit Document Feedback SYSTEM CONTROL REGISTER SYS_PARAMETER, address 0x05h DCD OUTPUT VOLTAGE SLEW RATE CONTROL REGISTER DCD_SRCTL, address 0x06h TABLE 7. SYS_PARAMETER REGISTER BIT NAME ACCESS RESET DESCRIPTION B7 - - 0 Reserved B6 I2C_EN R/W 0 I2C function enable. 0-disabled; 1-enabled B5 DCDPOR_1 R/W 1 DCDPOR Delay Time Setting, DCDPOR[1:0]: 00 to 1ms 01 to 50ms 10 to 150ms 11 to 200m B4 DCDPOR_0 R/W 0 B3 LDO2_EN R/W 1 LDO2 enable selection. 0-disable, 1-enable. B2 LDO1_EN R/W 1 LDO1 enable selection. 0-disable, 1-enable B1 DCD2_EN R/W 1 DCD2 enable selection. 0-disable, 1-enable. B0 DCD1_EN R/W 1 DCD1 enable selection. 0-disable, 1-enable TABLE 8. BIT NAME ACCESS RESET DESCRIPTION B7 DCD2SR_2 R/W 0 DCD2 Slew Rate Setting, DCD2SR[2:0]: 000 to 0.225mV/µs 001 to 0.45mV/µs 010 to 0.90mV/µs 011 to 1.8mV/µs 100 to 3.6mV/µs 101 to 7.2mV/µs 110 to 14.4mV/µs 111 to 28.8mV/µs B6 DCD2SR_1 R/W 0 B5 DCD2SR_0 R/W 1 B4 Reserve - 0 Reserved B3 DCD1SR_2 R/W 0 DCD1 Slew Rate Setting, DCD1SR[2:0]: 000 to 0.225mV/µs 001 to 0.45mV/µs 010 to 0.90mV/µs 011 to 1.8mV/µs 100 to 3.6mV/µs 101 to 7.2mV/µs 110 to 14.4mV/µs 111 to 28.8mV/µs B2 DCD1SR_1 R/W 0 B1 DCD1SR_0 R/W 1 B0 Reserve - 0 Reserved |
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