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ISL1561IRZ データシート(PDF) 11 Page - Intersil Corporation

部品番号 ISL1561IRZ
部品情報  Fixed Gain Dual Port Class-G Differential xDSL Line Driver
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メーカー  INTERSIL [Intersil Corporation]
ホームページ  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

ISL1561IRZ データシート(HTML) 11 Page - Intersil Corporation

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ISL1561
11
FN7941.1
February 26, 2013
Boost Control
Table 2 summarizes the logic of register MSB on boost operations followed by Figure 29 with the recommended look ahead timing for
the boost signal.
TABLE 1. SERIAL TIMING DIAGRAM
PARAMETER
RECOMMENDED OPERATING RANGE
DESCRIPTION
t
≥100ns
Clock Period
tr/tf
0.05*t
Clock Rise/Clock Fall
tHC
≥7ns
Data Hold Time
tSD
≥10ns
Data Setup Time
tHC
≥2.8ns
CS Hold Time
tSC
≥0.5ns
CS Setup Time
tW
0.50*t
Clock Pulse Width
TABLE 2. REGISTER MSB ON BOOST OPERATION
Reg3 8’h[7]
Reg7 8’h[7]
BOOST PIN
BOOST OPERATION
0X
1
1
X0
1
1
11
X
0
XX
0
0
NOTE: X = do not care
FIGURE 29. SERIAL TIMING DIAGRAM
td
BOOST
SIGNAL
TABLE 3. EXTERNAL BOOST SIGNAL TIMING PARAMETERS
PARAMETER
RECOMMENDED OPERATING RANGE
DESCRIPTION
td
100ns
Look ahead boost


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