ISLA112P25M

8

FN7646.1

November 17, 2011

Word Error Rate

WER

Full Power Bandwidth

FPBW

1.3

GHz

NOTES:

4. For min and max parameter limits, refer to DSCC drawing number V62/10609.

5. To ensure device accuracy the measurement temperature is to be within 60°C of the calibration temperature.

on each digital output.

7. See Nap /Sleep Mode description on page 17 for more details.

8. The DLL Range setting must be changed for low speed operation. See “Serial Peripheral Interface” on page 20 for more detail.

9. AC Specifications apply after internal calibration of the ADC is invoked at the given sample rate and temperature. Refer to

“Power-On Calibration” on page 14 and “User-Initiated Reset” on page 15 for more details.

speed grade). (Continued)

PARAMETER

SYMBOL

CONDITIONS

MIN

(Note 4)

TYP

MAX

(Note 4) UNITS

Digital Specifications

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

INPUTS

Input Current High (SDIO, RESETN)

1

µA

Input Current Low (SDIO, RESETN)

-12

µA

Input Voltage High (SDIO, RESETN)

1.8

V

Input Voltage Low (SDIO, RESETN)

0V

Input Current High (OUTMODE, NAPSLP, CLKDIV,

OUTFMT) (Note 10)

25

µA

Input Current Low (OUTMODE, NAPSLP, CLKDIV,

OUTFMT)

25

µA

Input Capacitance

3pF

LVDS OUTPUTS

Differential Output Voltage

3mA Mode

620

Output Offset Voltage

3mA Mode

965

mV

Output Rise Time

500

ps

Output Fall Time

500

ps

CMOS OUTPUTS

Voltage Output High

OVDD - 0.1

V

Voltage Output Low

0.1

V

Output Rise Time

1.8

ns

Output Fall Time

1.4

ns