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LM10500 データシート(PDF) 6 Page - Texas Instruments

部品番号 LM10500
部品情報  5A Step-Down Energy Management Unit (EMU) With PowerWise Adaptive Voltage Scaling (AVS)
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ホームページ  http://www.ti.com
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LM10500 データシート(HTML) 6 Page - Texas Instruments

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LM10500
SNVS630G – SEPTEMBER 2009 – REVISED MARCH 2013
www.ti.com
Thermal Properties
Junction Temperature
−40 °C to +125 °C
Ambient Temperature (1)
−40 °C to +85 °C
Junction-to-Ambient Thermal
Resistance (
θJA)
(2)
32.4 °C/W
(1)
In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may
have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP =
125°C), the maximum power dissipation of the device in the application (PD-MAX) and the junction-to ambient thermal resistance of the
part/package in the application (
θJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (θJA × PD-MAX).
(2)
Junction-to-ambient thermal resistance (
θJA) is taken from a thermal modeling result, performed under the conditions and guidelines set
forth in the JEDEC standard JESD51-7. The test board is a 4-layer standard JEDEC thermal test board or 4LJEDEC, 4" x 3" in size,
with a 3 by 3 array of thermal vias. The board has two embedded copper layers which cover roughly the same size as the board. The
copper thickness for the four layers, starting from the top one, is 2 oz./1oz./1oz./2 oz. For WQFN, thermal vias are placed between the
die attach pad in the 1st. copper layer and 2nd. copper layer. Detailed description of the board can be found in JESD 51-7. Ambient
temperature in the simulation is 22°C, still air. Power dissipation is 1W. The value of
θJA of this product can vary significantly depending
on PCB material, layout, and environmental conditions. In applications with high power dissipation (e.g. high VOUT, high IOUT), special
care must be paid to thermal dissipation issues. For more information on these topics, please refer to Application Note AN-1187:
Leadless Leadframe Package (LLP) SNOA401.
General Electrical Characteristics
(1) (2)
Specifications with standard typeface are for TJ = 25 °C, and those in boldface type apply over the full Operating
Temperature Range (TJ = −40 °C to 125 °C). Unless otherwise specified, VPVIN = VAVIN = 12 V, VOUT = 1.2 V.
Symbol
Parameter
Remarks
Min
Typ
Max
Unit
Feedback Pin Factory
LM10500SQ-0.8
0.788
0.8
0.812
VFB-default
Default Voltage. All
LM10500SQ-1.0
0.985
1.0
1.015
Registers in Default States
V
Maximum Feedback
VFB-range-top
Voltage Code = R0 – R9 = 7FH
1.0
Voltage
VFB-range-bottom
Minimum Feedback Voltage Voltage Code = R0 – R9 = 00H
0.6
Bit Length of The Feedback
Resolution
VFB = 0.6 V to 1 V
7
bit
Voltage DAC
Differential Non-Linearity of
DNL
VFB = 0.6 V to 1 V
0.5
LSB
VFB DAC
Integrated Non-Linearity of
INL
VFB = 0.6 V to 1 V
1
LSB
VFB DAC
ΔVOUT/ΔIOUT
Load Regulation
IOUT = 0.1 A to 5 A
0.02
%/A
ΔVOUT/ΔVIN
Line Regulation
VIN = 3.0 V to 18 V
0.01
%/V
High Side Switch On-Time
RDS-ON-HS
IDS-HS = 5 A
44
Resistance
m
Low Side Switch On-Time
RDS-ON-LS
IDS-LS = 5 A
22
Resistance
High Side Switch Current
ICL-HS
High-Side FET
5.9
7
7.87
Limit
Low Side Switch Current
ICL-LS
Low-Side FET(3)
5.9
8
10.2
A
Limit
Low Side Switch Negative
INEG-CL-LS
Low-Side FET
-7
-4.1
-1.64
Current Limit
Shutdown Quiescent
VAVIN = V PVIN = 5 V
0.1
2
ISD
Current, AVIN is Connected
µA
VAVIN = VPVIN = 18 V
1
4.1
to PVIN, VEN = 0
Quiescent Current With
Iq
Switcher On, No Load,
VAVIN = VPVIN = 18 V
9
9.7
mA
DCM Operation
Feedback Pin Input Bias
IFB
VFB = 1.0 V
1
nA
Current
(1)
All limits are ensured by design, test and/or statistical analysis. All electrical characteristics having room-temperature limits are tested
during production with TJ = 25°C. All hot and cold limits are ensured by correlating the electrical characteristics to process and
temperature variations and applying statistical process control.
(2)
Capacitors: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) are used in setting electrical characteristics.
(3)
The low side switch current limit is ensured to be higher than the high side switch current limit.
6
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