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LM10500 データシート(PDF) 8 Page - Texas Instruments |
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LM10500 データシート(HTML) 8 Page - Texas Instruments |
8 / 40 page LM10500 SNVS630G – SEPTEMBER 2009 – REVISED MARCH 2013 www.ti.com General Electrical Characteristics (1) (2) (continued) Specifications with standard typeface are for TJ = 25 °C, and those in boldface type apply over the full Operating Temperature Range (TJ = −40 °C to 125 °C). Unless otherwise specified, VPVIN = VAVIN = 12 V, VOUT = 1.2 V. Symbol Parameter Remarks Min Typ Max Unit IOL- PWROK PWROK Sink Current VOL = 0.2 V 3 mA IOH- PWROK PWROK Leakage Current VOH = 18 V 460 nA PWI I/O: SPWI, SCLK. The VPWI pin is powered from an external source, VPWI range = 1.8V-10% to 3.3V+10% VPWI Pin Voltage Ramping VPWI Slew Rate See(4) 500 µs Rate VIH Logic Input High % of VPWI 80 % VIL Logic Input Low % of VPWI 20 % Input Leakage Current, Pin SPWI, SCLK Pins Have Internal IIH +5 Driven High (VPWI) Pulldowns µA Input Leakage Current, Pin IIL -1 Driven Low VOH Logic Output High Sourcing 1mA, % of VPWI 80 % VOL Logic Output Low Sinking 1mA, % of VPWI 10 Pull-down resistance for RPD-PWI SPWI, SCLK 0.5 1 2 M Ω PWI signals Maximum PWI SCLK FSCLK-MAX SCLK 15 MHz Frequency SPWI Data Change Time to TD % of SCLK Cycle, FSCLK ≤ 15 MHz (5) 27 Valid Value TS SPWI Data Setup Time % of SCLK Cycle, FSCLK ≤ 15 MHz (5) 14 % TH SPWI Data Hold Time % of SCLK Cycle, FSCLK ≤ 15 MHz (5) 39 SPWI Data Drive Release TXZ % of SCLK Cycle, FSCLK ≤ 15 MHz (5) 27 Time THERMAL SHUTDOWN TSD Thermal Shutdown See(6) 160 °C Thermal Shutdown TSD-HYS See(6) 10 °C Hysteresis (4) Recommend not to exceed 500 µs ramp time. (5) Ensured by design. For more details, please refer to PWI 1.0 Specifications or PWI 2.0 Specifications. (6) Ensured by design. 8 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: LM10500 |
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同様の説明 - LM10500 |
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