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MTV16N50E データシート(PDF) 1 Page - ON Semiconductor |
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MTV16N50E データシート(HTML) 1 Page - ON Semiconductor |
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1 / 10 page  © Semiconductor Components Industries, LLC, 2006 August, 2006 − Rev. 1 1 Publication Order Number: MTV16N50E/D MTV16N50E Advance Information TMOS E−FET.™ Power Field Effect Transistor D3PAK for Surface Mount N−Channel Enhancement−Mode Silicon Gate This high voltage MOSFET uses an advanced termination scheme to provide enhanced voltage−blocking capability without degrading performance over time. In addition, this advanced TMOS E−FET is designed to withstand high energy in the avalanche and commutation modes. The new energy efficient design also offers a drain−to−source diode with a fast recovery time. Designed for high speed switching applications in power supplies, converters, PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. • Robust High Voltage Termination • Avalanche Energy Specified • Source−to−Drain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode • Diode is Characterized for Use in Bridge Circuits • IDSS and VDS(on) Specified at Elevated Temperature MAXIMUM RATINGS (TC = 25°C unless otherwise noted) Rating Symbol Value Unit Drain−to−Source Voltage VDSS 500 Vdc Drain−to−Gate Voltage (RGS = 1.0 MΩ) VDGR 500 Vdc Gate−to−Source Voltage — Continuous VGS ±20 Vdc Drain Current — Continuous Drain Current — Continuous @ 100°C Drain Current — Single Pulse (tp ≤ 10 μs) ID ID IDM 16 9.0 60 Adc Apk Total Power Dissipation Derate above 25°C Total Power Dissipation @ TA = 25°C (1) PD 180 1.4 2.0 Watts W/°C Watts Operating and Storage Temperature Range TJ, Tstg −55 to 150 °C Single Pulse Drain−to−Source Avalanche Energy — Starting TJ = 25°C (VDD = 50 Vdc, VGS = 10 Vdc, Peak IL = 16 Apk, L = 6.7 mH, RG = 25 Ω ) EAS 860 mJ Thermal Resistance — Junction to Case Thermal Resistance — Junction to Ambient Thermal Resistance — Junction to Ambient (1) RθJC RθJA RθJA 0.7 62.5 35 °C/W Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds TL 260 °C (1) When surface mounted to an FR4 board using the minimum recommended pad size. This document contains information on a new product. Specifications and information herein are subject to change without notice. http://onsemi.com TMOS POWER FET 16 AMPERES, 500 VOLTS RDS(on) = 0.40 W D3PAK Surface Mount CASE 433−01 Style 2 ® D S G N−Channel |
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