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LM10011 データシート(PDF) 4 Page - Texas Instruments |
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LM10011 データシート(HTML) 4 Page - Texas Instruments |
4 / 24 page LM10011 SNVS822A – DECEMBER 2012 – REVISED NOVEMBER 2014 www.ti.com 6.2 Handling Ratings MIN MAX UNIT Tstg Storage temperature range –65 150 °C Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, 2 all pins(1) V(ESD) Electrostatic discharge kV Charged device model (CDM), per JEDEC specification 1 JESD22-C101, all pins(2) (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VDD 2.97 5.5 V IDAC_OUT –0.3 VDD – 1.75 V VIDA, VIDB, VIDC, VIDS, EN, MODE –0.3 5.5 V Junction Temperature −40 125 °C Ambient Temperature −40 125 °C 6.4 Thermal Information LM10011 THERMAL METRIC(1) DSC UNIT 10 PINS RθJA Junction-to-ambient thermal resistance(2) 52.1 RθJC(top) Junction-to-case (top) thermal resistance(3) 30.6 RθJB Junction-to-board thermal resistance(4) 26.8 °C/W ψJT Junction-to-top characterization parameter(5) 0.9 ψJB Junction-to-board characterization parameter(6) 26.9 RθJC(bot) Junction-to-case (bottom) thermal resistance(7) 7.7 (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. (2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. (3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC- standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. (4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. (5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7). (6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7). (7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. Spacer 4 Submit Documentation Feedback Copyright © 2012–2014, Texas Instruments Incorporated Product Folder Links: LM10011 |
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同様の説明 - LM10011_15 |
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