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TMP112AQDRLRQ1 データシート(PDF) 5 Page - Texas Instruments |
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TMP112AQDRLRQ1 データシート(HTML) 5 Page - Texas Instruments |
5 / 33 page TMP112-Q1 www.ti.com SLOS887D – SEPTEMBER 2014 – REVISED DECEMBER 2015 Electrical Characteristics (continued) At TA = 25°C and V+ = 1.4 to 3.6 V, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLY Operating supply range 1.4 3.6 V Serial bus inactive, CR1 = 1, CR0 = 0 7 10 (default) IQ Average quiescent current Serial bus active, SCL frequency μA 15 (ƒ(SCL)) = 400 kHz Serial bus active, ƒ(SCL) = 3.4 MHz 85 Serial bus inactive 0.5 1 ISD Shutdown current Serial bus active, ƒ(SCL) = 400 kHz 10 μA Serial bus active, ƒ(SCL) = 3.4 MHz 80 6.6 Specifications for User-Calibrated Systems For additional information on the slopes listed in this table, see the Calibrating for Improved Accuracy section. PARAMETER CONDITION MIN MAX UNIT V+ = 3.3, –40°C to 25°C –7 0 m°C/°C Average Slope V+ = 3.3, 25°C to 85°C 0 5 m°C/°C (Temperature Error vs Temperature)(1) V+ = 3.3, 85°C to 125°C 0 8 m°C/°C (1) User-calibrated temperature accuracy can be within ±1LSB because of quantization noise. 6.7 Timing Requirements See the Timing Diagrams section for timing diagrams. HIGH-SPEED FAST MODE MODE UNIT MIN MAX MIN MAX ƒ(SCL) SCL operating frequency V+ 0.001 0.4 0.001 2.85 MHz Bus-free time between STOP and START t(BUF) 600 160 ns condition Hold time after repeated START condition. t(HDSTA) 600 160 ns After this period, the first clock is generated. See Two-Wire Timing Diagrams t(SUSTA) repeated start condition setup time 600 160 ns t(SUSTO) STOP condition setup time 600 160 ns t(HDDAT) Data hold time 100 900 25 105 ns t(SUDAT) Data setup time 100 25 ns V+ , see Two-Wire Timing t(LOW) SCL-clock low period 1300 210 ns Diagrams t(HIGH) SCL-clock high period See Two-Wire Timing Diagrams 600 60 ns tFD Data fall time See Two-Wire Timing Diagrams 300 80 ns See Two-Wire Timing Diagrams 300 ns tRD Data rise time SCLK ≤ 100 kHz, see Two-Wire 1000 ns Timing Diagrams tFC Clock fall time See Two-Wire Timing Diagrams 300 40 ns tRC Clock rise time See Two-Wire Timing Diagrams 300 40 ns Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: TMP112-Q1 |
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