TS7003 datasheet(10/15 Pages) SILABS

部品番号	TS7003

部品情報	A 300ksps, Single-supply, 12-Bit Serial-output ADC

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メーカー	SILABS [Silicon Laboratories]

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TS7003

Page 10

TS7003 Rev. 1.0

Figure 6: TS7003 Shutdown Operation.

Using the ADC’s SHDN to Reduce Operating

Supply Current

Power consumption can be reduced significantly by

turning off the TS7003 in between conversions.

Figure 5 illustrates the TS7003’s average supply

current versus conversion rate. The wake-up delay

time (tWAKE) is the time from when the SHDN pin is

deasserted to the time when a conversion may be

initiated (Refer to Figure 6). This delay time depends

on how long the ADC was in shutdown (Refer to

Figure 7) because the external 4.7

μF reference

bypass

capacitor

is

discharged

slowly

when

SHDN = 0.

Timing and Control Details

The CS and SCLK digital inputs control the TS7003’s

conversion-start

and

data-read

operations.

The

ADC’s serial-interface operations are illustrated in

Figures 8 and 9.

A CS high-to-low transition initiates the conversion

sequence - the input track-and-hold samples the input

signal level, the ADC begins to convert, and the

DOUT pin changes state from high impedance to

logic low. The external SCLK signal is used to drive

the conversion process and is also used to transfer

the converted data out of the ADC as each bit of

conversion is determined.

The SCLK signal transfers data after a low-to-high

transition of the third (3rd) SCLK pulse. After each

subsequent SCLK rising edge, transitions on the

DOUT pin occur in 20ns. The third rising clock edge

produces the MSB of the conversion at DOUT,

followed by the remaining bits. Since there are twelve

data bits and three leading zeros, at least fifteen

rising clock edges are needed to transfer the entire

data stream. Extra SCLK pulses occurring after the

conversion result has been completely transferred out

and, before to a new, low-to-high transition on CS,

produce a string trailing zeros at DOUT. In addition,

the extra SCLK pulses have no effect on converter

operation.

Minimum conversion cycle time can be accomplished

by: (a) toggling the CS pin high after reading the

conversion result’s LSB; and (b), after the specified

minimum time defined by tCS has elapsed, toggling

the CS pin low again to initiate the next conversion.

Output Data Coding and Transfer Function

Conversion results at the TS7003’s DOUT pin are

straight binary data. Figure 10 illustrates the nominal

transfer function where code transitions occur halfway

between

successive

integer

LSB

values.

If

VREF = +2.500V, then 1 LSB = 610

μV or 2.500V/4096.

CONVERSION RATE - ksps

VDD = 3V

DOUT = FS

RL = ∞

CL = 10pF

100

10

1

0.1

1

100

1k

10

1k

Figure 5: TS7003 Supply Current vs Conversion Rate

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同様の説明 - TS7003

メーカー	部品番号	データシート	部品情報
Touchstone Semiconducto...	TS7003	170Kb / 2P	A 300ksps, Single-supply, 12-Bit Serial-output ADC
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