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STAP16DPPS05XTTR データシート(PDF) 10 Page - STMicroelectronics |
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STAP16DPPS05XTTR データシート(HTML) 10 Page - STMicroelectronics |
10 / 33 page Electrical characteristics STAP16DPPS05 10/33 DocID024306 Rev 6 VDD = 5 V, Tj = 25 °C, unless otherwise specified. Table 8. Switching characteristics(1)(2) Symbol Parameter Test conditions Min. Typ. Max. Unit fclk Clock frequency Cascade operation 30 MHz tPLH1 CLK-OUTn, LE/DM1 = H, OE/DM2 = L VIH = VDD VIL = GND CL = 10 pF IO = 20 mA VL = 3.0 V RL = 60 Ω VDD = 3.3 V 55 90 ns VDD = 5 V 30 50 tPLH2 LE/DM1-OUTn, OE/DM2 = L VDD = 3.3 V 48 80 ns VDD = 5 V 30 45 tPLH3 OE/DM2-OUTn, LE\DM1 = H VDD = 3.3 V 70 120 ns VDD = 5 V 45 65 tPLH CLK-SDO VDD = 3.3 V 21 35 ns VDD = 5 V 15 25 tPHL1 CLK-OUTn, LE/DM1 = H, OE/DM2 = L VDD = 3.3 V 28 35 ns VDD = 5 V 22 40 tPHL2 LE/DM1-OUTn, OE/DM2 = L VDD = 3.3 V 13 35 ns VDD = 5 V 12 18 tPHL3 OE/DM2-OUTn, LE/DM1 = H VDD = 3.3 V 24 35 ns VDD = 5 V 21 30 tPHL CLK-SDO VDD = 3.3 V 24 40 ns VDD = 5 V 17 25 tON Output rise time 10~90% of voltage waveform VDD = 3.3 V 30 55 ns VDD = 5 V 10 20 tOFF Output fall time 90~10% of voltage waveform VDD = 3.3 V 4 10 ns VDD = 5 V 3 8 tr CLK rise time (3) 5 µs tf CLK fall time (3) 5 1. All table limits are guaranteed by design. 2. Not tested in production. 3. If devices are connected in cascade and tr or tf is large, it may be critical to achieve the timing required for data transfer between two cascaded devices. |
同様の部品番号 - STAP16DPPS05XTTR |
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同様の説明 - STAP16DPPS05XTTR |
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