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TL16C752D-Q1 データシート(PDF) 9 Page - Texas Instruments

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部品番号 TL16C752D-Q1
部品情報  Dual UART With 64-Byte FIFO
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メーカー  TI1 [Texas Instruments]
ホームページ  http://www.ti.com
Logo TI1 - Texas Instruments

TL16C752D-Q1 データシート(HTML) 9 Page - Texas Instruments

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Valid Address
t 6s
A[2:0]
CS
D[7:0]
Valid Address
t
6h
t 13w
t 6h
t 6s
t
13w
t 15d
IOW
t
16h
t
16h
Valid Data
Valid Data
t 16s
t 16s
9
TL16C752D-Q1
www.ti.com
SLLSET4 – FEBRUARY 2016
Product Folder Links: TL16C752D-Q1
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
7.6 Timing Requirements
TA = 0°C to 70°C, VCC = 1.8 V to 5 V ±10% (unless otherwise noted)
LIMITS
UNIT
1.8 V
2.5 V
3.3 V
5 V
MIN MAX
MIN MAX
MIN MAX
MIN MAX
tRESET Reset pulse width
200
200
200
200
ns
CP
CP clock period
63
42
32
20
ns
t3w
Oscillator or clock speed
16
24
32
48
MHz
t6s
Address setup time
20
15
10
5
ns
t6h
Address hold time
See Figure 1 and Figure 2
15
10
7
5
ns
t7w
IOR strobe width
See Figure 1 and Figure 2
85
70
50
40
ns
t9d
Read cycle delay
See Figure 2
85
70
60
50
ns
t12d
Delay from IOR to data
See Figure 2
65
50
35
25
ns
t12h
Data disable time
35
25
20
15
ns
t13w
IOW strobe width
See Figure 1
85
70
50
40
ns
t15d
Write cycle delay
See Figure 1
85
70
60
50
ns
t16s
Data setup time
See Figure 1
40
30
20
15
ns
t16h
Data hold time
See Figure 1
35
25
15
10
ns
t17d
Delay from IOW to output
50-pF load, see Figure 3
60
40
30
20
ns
t18d
Delay to set interrupt from
MODEM input
50-pF load, see Figure 3
70
55
45
35
ns
t19d
Delay to reset interrupt from IOR 50-pF load
80
55
40
30
ns
t20d
Delay from stop to set interrupt
See Figure 4
1
1
1
1
baudrate
t21d
Delay from IOR to reset interrupt 50-pF load, see Figure 4
55
45
35
25
ns
t22d
Delay from stop to interrupt
See Figure 7
1
1
1
1
baudrate
t23d
Delay from initial IOW reset to
transmit start
See Figure 7
8
24
8
24
8
24
8
24
baudrate
t24d
Delay from IOW to reset
interrupt
See Figure 7
75
45
35
25
ns
t25d
Delay from stop to set RXRDY
See Figure 5 and Figure 6
1
1
1
1
baudrate
t26d
Delay from IOR to reset RXRDY
See Figure 5 and Figure 6
1
1
1
1
μs
t27d
Delay from IOW to set TXRDY
See Figure 8 and Figure 9
70
60
50
40
ns
t28d
Delay from start to reset TXRDY
See Figure 8 and Figure 9
16
16
16
16
baudrate
Figure 1. General Write Timing


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