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STAP08DP05 データシート(PDF) 9 Page - STMicroelectronics |
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STAP08DP05 データシート(HTML) 9 Page - STMicroelectronics |
9 / 28 page DocID024305 Rev 6 9/28 STAP08DP05 Switching characteristics 28 5 Switching characteristics VDD = 5 V, Tj = 25 °C, unless otherwise specified. Table 8. Switching characteristics(1)(2) Symbol Parameter Test conditions Min Typ Max Unit fclk Clock frequency Cascade operation 30 MHz tPLH1 CLK-OUTn LE\DM1 = H OE\DM2 = L Propagation delay time (“L” to “H”) VIH = VDD VIL = GND CL = 10 pF Io = 20 mA VL = 3 V REXT = 1 K Ω RL = 60 Ω VDD = 3.3 V 36 50 ns VDD = 5 V 19 25 tPLH2 LE\DM1-OUTn OE\DM2 = L VDD = 3.3 V 38 50 ns VDD = 5 V 21 30 tPLH3 OE\DM2-OUTn LE\DM1 = H VDD = 3.3 V 42 55 ns VDD = 5 V 23 30 tPLH CLK - SDO VDD = 3.3 V 22 30 ns VDD = 5 V 18 25 tPHL1 CLK-OUTn LE\DM1 = H OE\DM2 = L Propagation delay time (“H” to “L”) VDD = 3.3 V 9 12 ns VDD = 5 V 5 7 tPHL2 LE\DM1-OUTn OE\DM2 = L VDD = 3.3 V 4 6 ns VDD = 5 V 3 5 tPHL3 OE\DM2-OUTn LE\DM1 = H VDD = 3.3 V 6 8 ns VDD = 5 V 3 5 tPHL CLK - SDO VDD = 3.3 V 25 33 ns VDD = 5 V 20 26 tON Output rise time 10~90% of voltage waveform VDD = 3.3 V 30 40 ns VDD = 5 V 15 20 tOFF Output fall time 90~10% of voltage waveform VDD = 3.3 V 7 10 ns VDD = 5 V 6 8 tr CLK rise time (3) 5 µs tf CLK fall time (3) 5 1. All table limits are guaranteed by design. 2. Not tested in production. 3. If devices are connected in cascade and tr or tf is large, it may be critical to achieve the timing required for data transfer between two cascaded devices. |
同様の部品番号 - STAP08DP05 |
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同様の説明 - STAP08DP05 |
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