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74F190SC データシート(PDF) 2 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
部品番号 74F190SC
部品情報  Up/Down Decade Counter with Preset and Ripple Clock
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メーカー  NSC [National Semiconductor (TI)]
ホームページ  http://www.national.com
Logo NSC - National Semiconductor (TI)

74F190SC データシート(HTML) 2 Page - National Semiconductor (TI)

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Unit LoadingFan Out
54F74F
Pin Names
Description
UL
Input IIH IIL
HIGHLOW
Output IOH IOL
CE
Count Enable Input (Active LOW)
1030
20 mA b18 mA
CP
Clock Pulse Input (Active Rising Edge)
1010
20 mA b06 mA
P0–P3
Parallel Data Inputs
1010
20 mA b06 mA
PL
Asynchronous Parallel Load Input (Active LOW)
1010
20 mA b06 mA
U D
UpDown Count Control Input
1010
20 mA b06 mA
Q0–Q3
Flip-Flop Outputs
50333
b
1 mA20 mA
RC
Ripple Clock Output (Active LOW)
50333
b
1 mA20 mA
TC
Terminal Count Output (Active HIGH)
50333
b
1 mA20 mA
Functional Description
The ’F190 is a synchronous updown BCD decade counter
containing four edge-triggered flip-flops with internal gating
and steering logic to provide individual preset count-up and
count-down operations It has an asynchronous parallel
load capability permitting the counter to be preset to any
desired number When the Parallel Load (PL) input is LOW
information present on the Parallel Data inputs (P0–P3)is
loaded into the counter and appears on the Q outputs This
operation overrides the counting functions as indicated in
the Mode Select Table A HIGH signal on the CE input inhib-
its counting When CE is LOW internal state changes are
initiated synchronously by the LOW-to-HIGH transition of
the clock input The direction of counting is determined by
the U D input signal as indicated in the Mode Select Table
CE and U D can be changed with the clock in either state
provided only that the recommended setup and hold times
are observed
Two types of outputs are provided as overflowunderflow
indicators The Terminal Count (TC) output is normally LOW
and goes HIGH when a circuit reaches zero in the count-
down mode or reaches 9 in the count-up mode The TC
output will then remain HIGH until a state change occurs
whether by counting or presetting or until U D is changed
The TC output should not be used as a clock signal be-
cause it is subject to decoding spikes The TC signal is also
used internally to enable the Ripple Clock (RC) output The
RC output is normally HIGH When CE is LOW and TC is
HIGH the RC output will go LOW when the clock next goes
LOW and will stay LOW until the clock goes HIGH again
This feature simplifies the design of multistage counters
For a discussion and illustrations of the various methods of
implementing multistage counters please see the ’F191
data sheet
RC Truth Table
Inputs
Output
CE
TC
CP
RC
LH
HX
X
H
XL
X
H
TC is generated internally
H e HIGH Voltage Level
L e LOW Voltage Level
X e Immaterial
L e LOW-to-HIGH Clock Transition
e
LOW Pulse
Mode Select Table
Inputs
Mode
PL
CE
U D
CP
HL
L
L
Count Up
HL
H
L
Count Down
L
X
X
X
Preset (Asyn)
H
H
X
X
No Change (Hold)
State Diagram
TLF9494 – 5
2


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同様の説明 - 74F190SC

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