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LM20143MHE データシート(PDF) 4 Page - Texas Instruments |
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LM20143MHE データシート(HTML) 4 Page - Texas Instruments |
4 / 36 page LM20143, LM20143-Q1 SNVS528H – OCTOBER 2007 – REVISED JANUARY 2016 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings See (1) MIN MAX UNIT AVIN, PVIN, EN, PGOOD, SS/TRK, COMP, FB, RT Voltages from indicated pins to GND –0.3 6 V Power Dissipation(2) 2.6 W Junction Temperature 150 °C Lead Temperature (Soldering, 10 sec) 260 °C Storage Temperature –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The maximum allowable power dissipation is a function of the maximum junction temperature, TJ_MAX, the junctions-to-ambient thermal resistance, θJA, and the ambient temperature, TA. The maximum allowable power dissipation at any ambient temperature is calculated using: PD_MAX = (TJ_MAX – TA) / θJA. The maximum power dissipations of 2.6 W is determined using TA = 25°C, θJA = 38°C/W, and TJ_MAX = 125°C. 6.2 ESD Ratings VALUE UNIT Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V(ESD) Electrostatic discharge V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions MIN MAX UNIT PVIN, AVIN to GND 2.95 5.5 V Junction Temperature −40 125 °C 6.4 Thermal Information LM20143 THERMAL METRIC(1) PWP (HTSSOP) UNIT 16 PINS RθJA Junction-to-ambient thermal resistance (2) 39.3 °C/W RθJC(top) Junction-to-case (top) thermal resistance (3) 20.3 °C/W RθJB Junction-to-board thermal resistance 9.9 °C/W ψJT Junction-to-top characterization parameter 0.6 °C/W ψJB Junction-to-board characterization parameter 9.9 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 12.1 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. (2) On JEDEC 4-Layer test board (JESD 51-7) with eight (8) thermal vias. (3) θJC refers to center of the Exposed Pad on the bottom of the package as the case. 4 Submit Documentation Feedback Copyright © 2007–2016, Texas Instruments Incorporated Product Folder Links: LM20143 LM20143-Q1 |
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