AD7175-8

Data Sheet

Rev. 0 | Page 6 of 64

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

Full Operating Mode

All buffers disabled, external clock and

reference, AVDD2 = 2 V, IOVDD = 2 V

21

mW

All buffers disabled, external clock and

reference, all supplies = 5 V

42

mW

All buffers disabled, external clock and

reference, all supplies = 5.5 V

52

mW

All buffers enabled, internal clock and

reference, AVDD2 = 2 V, IOVDD = 2 V

82

mW

All buffers enabled, internal clock and

reference, all supplies = 5 V

105

mW

All buffers enabled, internal clock and

reference, all supplies = 5.5 V

136

mW

Standby Mode

Internal reference off, all supplies = 5 V

150

µW

Internal reference on, all supplies = 5 V

2.2

mW

Power-Down Mode

Full power-down, all supplies = 5 V

25

50

µW

calibration reduces the gain error to the order of the noise for the programmed output data rate.

TIMING CHARACTERISTICS

Table 2.

Parameter

Unit

SCLK

t

3

25

ns min

SCLK high pulse width

t

4

25

ns min

SCLK low pulse width

READ OPERATION

t

1

0

ns min

CS falling edge to DOUT/RDY active time

15

ns max

IOVDD = 4.75 V to 5.5 V

40

ns max

IOVDD = 2 V to 3.6 V

t

2

3

0

ns min

12.5

ns max

IOVDD = 4.75 V to 5.5 V

25

ns max

IOVDD = 2 V to 3.6 V

t

5

5

2.5

ns min

Bus relinquish time after CS inactive edge

20

ns max

t

6

0

ns min

SCLK inactive edge to CS inactive edge

t

7

10

ns min

SCLK inactive edge to DOUT/RDY high/low

WRITE OPERATION

t

8

0

ns min

CS falling edge to SCLK active edge setup time4

t

9

8

ns min

Data valid to SCLK edge setup time

t

10

8

ns min

Data valid to SCLK edge hold time

t

11

5

ns min

CS rising edge to SCLK edge hold time

while DOUT/RDY is high, although care must be taken to ensure that subsequent reads do not occur close to the next output update. If the continuous read feature is

enabled, the digital word can be read only once.